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#address-cells#size-cellsmodelcompatiblegpio0gpio1serial0serial1interrupts-extendedcontrollerinterrupt-parentpcie-mem-aperturepcie-io-aperturerangesregclocksstatuscache-unifiedcache-levelarm,double-linefill-incrarm,double-linefill-wraparm,double-linefillprefetch-datainterrupts#interrupt-cellsinterrupt-controllerphandlepinctrl-namespinctrl-0clock-frequencygpio-controller#gpio-cellsreg-shiftreg-io-widthmarvell,pinsmarvell,functionreg-namesngpiosgpio-ranges#pwm-cells#clock-cells#phy-cellsmsi-controllerclock-namestx-csum-limitphyphy-modebuffer-managerbm,pool-longbm,pool-shortvcc-supplydmacap,memcpydmacap,xordmacap,memsetmarvell,crypto-sramsmarvell,crypto-sram-sizetarget-supplyinternal-memclock-output-namesmrvl,clk-delay-cyclesno-1-8-vbroken-cdwp-invertedbus-width#sound-dai-cellsusb-phyno-memory-wccell-indexspi-max-frequencym25p,fast-readdevice_typemsi-parentbus-rangeassigned-addressesinterrupt-namesinterrupt-map-maskinterrupt-mapmarvell,pcie-portmarvell,pcie-lanegpio-fan,speed-mapenable-methodstdout-pathregulator-nameregulator-min-microvoltregulator-max-microvoltenable-active-highgpioregulator-always-onregulator-boot-onvin-supply