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#address-cells#size-cellsmodelcompatibleenable-methoddevice_typeregnext-level-cachephandleinterrupt-parentinterruptsinterrupt-affinity#interrupt-cellsinterrupt-controllerranges#dma-cellsclocksclock-namesresetsreset-namesfpga-mgr#clock-cellsclock-frequencydiv-regfixed-dividerclk-gateclk-phasesnps,wr_osr_lmtsnps,rd_osr_lmtsnps,blenaltr,sysmgr-sysconinterrupt-namesmac-addresssnps,multicast-filter-binssnps,perfect-filter-entriestx-fifo-depthrx-fifo-depthsnps,axi-configstatusphy-modephy-addrtxd0-skew-pstxd1-skew-pstxd2-skew-pstxd3-skew-psrxd0-skew-psrxd1-skew-psrxd2-skew-psrxd3-skew-pstxen-skew-pstxc-skew-psrxdv-skew-psrxc-skew-psmax-frame-sizegpio-controller#gpio-cellssnps,nr-gpiosi2c-sda-falling-time-nsi2c-scl-falling-time-nsvref-supplypagesizenum-cstx-dma-channelrx-dma-channelspi-max-frequency#reset-cellscache-unifiedcache-levelprefetch-dataprefetch-instrarm,shared-overridecap-sd-highspeedcap-mmc-highspeedbroken-cdbus-widthreg-namesaltr,sdr-sysconaltr,ecc-parentcdns,fifo-depthcdns,fifo-widthcdns,trigger-addressaltr,modrst-offsetcpu1-start-addrreg-shiftreg-io-width#phy-cellsphysphy-namesdisable-over-currentethernet0serial0bootargsstdout-pathlabelregulator-nameregulator-min-microvoltregulator-max-microvolt