f8a(a ,Freescale i.MX8QXP MEK2fsl,imx8qxp-mekfsl,imx8qxpaliases =/bus@5b000000/ethernet@5b040000 G/bus@5b000000/ethernet@5b050000Q/bus@5d000000/gpio@5d080000W/bus@5d000000/gpio@5d090000]/bus@5d000000/gpio@5d0a0000c/bus@5d000000/gpio@5d0b0000i/bus@5d000000/gpio@5d0c0000o/bus@5d000000/gpio@5d0d0000u/bus@5d000000/gpio@5d0e0000{/bus@5d000000/gpio@5d0f0000/bus@5a000000/i2c@5a800000/bus@5a000000/i2c@5a810000/bus@5a000000/i2c@5a820000/bus@5a000000/i2c@5a830000/bus@5b000000/mmc@5b010000/bus@5b000000/mmc@5b020000/bus@5b000000/mmc@5b030000/bus@5d000000/mailbox@5d1b0000/bus@5d000000/mailbox@5d1c0000/bus@5d000000/mailbox@5d1d0000/bus@5d000000/mailbox@5d1e0000/bus@5d000000/mailbox@5d1f0000/bus@5a000000/serial@5a060000/bus@5a000000/serial@5a070000/bus@5a000000/serial@5a080000/bus@5a000000/serial@5a090000 /vpu@2c000000/vpu-core@2d080000 /vpu@2c000000/vpu-core@2d090000cpus cpu@0cpu2arm,cortex-a35psci @)6C@Ub szcpu@1cpu2arm,cortex-a35psci @)6C@Ub sz cpu@2cpu2arm,cortex-a35psci @)6C@Ub sz cpu@3cpu2arm,cortex-a35psci @)6C@Ub sz l2-cache02cache @+opp-table2operating-points-v2opp-9000000005B@Iopp-1200000000GIinterrupt-controller@51a00000 2arm,gic-v3 QQ   reserved-memory decoder-boot@84000000&encoder-boot@86000000 &decoder-rpc@92000000&dsp@92400000@&encoder-rpc@94400000@p&pmu2arm,cortex-a35-pmu psci 2arm,psci-1.0smcsystem-controller 2fsl,imx-scu -tx0rx0gip3$8power-controller2fsl,imx8qxp-scu-pdfsl,scu-pd?clock-controller2fsl,imx8qxp-clkfsl,scu-clkSpinctrl2fsl,imx8qxp-iomuxcfec1grp`5 4 & % ' ( ) * , - . / 0 1 2ioexprstgrp `Z!%isl29023grp `[!'lpi2c1grp`!!$lpuart0grp`o p usdhc1grp` A ! ! ! !!!!!!A+usdhc2grpT`A! !!!"!#!!-ocotp2fsl,imx8qxp-scu-ocotp keys"2fsl,imx8qxp-sc-keyfsl,imx-sc-keyitxokayrtc2fsl,imx8qxp-sc-rtcwatchdog"2fsl,imx8qxp-sc-wdtfsl,imx-sc-wdt<thermal-sensor*2fsl,imx8qxp-sc-thermalfsl,imx-sc-thermaltimer2arm,armv8-timer0   clock-xtal32k 2fixed-clockS xtal_32KHzclock-xtal24m 2fixed-clockSn6 xtal_24MHzthermal-zonescpu0-thermalctripstrip0passivetrip1 criticalcooling-mapsmap00 pmic-thermal0tripstrip0passive trip1H criticalcooling-mapsmap0 0 bus@58000000 2simple-bus XXclock-img-ipg 2fixed-clockS  img_ipg_clkjpegdec@58400000X@05678s #peripg/ ? (T2nxp,imx8qxp-jpgdecjpegenc@58450000XE01234s#peripg/? (T2nxp,imx8qxp-jpgencclock-controller@585d00002fsl,imx8qxp-lpcgX]Ssb0img_jpeg_dec_lpcg_clkimg_jpeg_dec_lpcg_ipg_clkT clock-controller@585f00002fsl,imx8qxp-lpcgX_Ssb0img_jpeg_enc_lpcg_clkimg_jpeg_enc_lpcg_ipg_clkTvpu@2c000000 ,,,Txokay2nxp,imx8qxp-vpumailbox@2d0000002fsl,imx6sx-mu- pTxokaymailbox@2d0200002fsl,imx6sx-mu- pTxokayvpu-core@2d080000-2nxp,imx8q-vpu-decoderT -tx0tx1rx$8xokay|vpu-core@2d090000-2nxp,imx8q-vpu-encoderT -tx0tx1rx$8xokay|bus@59000000 2simple-bus YYclock-audio-ipg 2fixed-clockS'audio_ipg_clkclock-controller@595800002fsl,imx8qxp-lpcgYXS s b4dsp_lpcg_adb_clkdsp_lpcg_ipg_clkdsp_lpcg_core_clkTclock-controller@595900002fsl,imx8qxp-lpcgYYSsbdsp_ram_lpcg_ipg_clkTdsp@596e80002fsl,imx8qxp-dspYns#ipgocramcore T-txdb0txdb1rxdb0rxdb108|xokaybus@5a000000 2simple-bus ZZclock-dma-ipg 2fixed-clockS' dma_ipg_clk!serial@5a060000Z s #ipgbaud /9?ĴT9xokay2fsl,imx8qxp-lpuartdefaultserial@5a070000Z s #ipgbaud /:?ĴT: xdisabled2fsl,imx8qxp-lpuartserial@5a080000Z s #ipgbaud /;?ĴT; xdisabled2fsl,imx8qxp-lpuartserial@5a090000Z  s   #ipgbaud /<?ĴT< xdisabled2fsl,imx8qxp-lpuartclock-controller@5a4600002fsl,imx8qxp-lpcgZFSs9!b'uart0_lpcg_baud_clkuart0_lpcg_ipg_clkT9clock-controller@5a4700002fsl,imx8qxp-lpcgZGSs:!b'uart1_lpcg_baud_clkuart1_lpcg_ipg_clkT:clock-controller@5a4800002fsl,imx8qxp-lpcgZHSs;!b'uart2_lpcg_baud_clkuart2_lpcg_ipg_clkT;clock-controller@5a4900002fsl,imx8qxp-lpcgZISs<!b'uart3_lpcg_baud_clkuart3_lpcg_ipg_clkT< i2c@5a800000Z@ s""#peripg /`?n6T` xdisabled$2fsl,imx8qxp-lpi2cfsl,imx7ulp-lpi2ci2c@5a810000Z@ s###peripg /a?n6Taxokay$2fsl,imx8qxp-lpi2cfsl,imx7ulp-lpi2c default$%i2c-mux@712nxp,pca9646nxp,pca9546 q &i2c@0 gpio@682maxim,max7322hi2c@1 i2c@2 pressure-sensor@60 2fsl,mpl3115`i2c@3 gpio@1a 2nxp,pca9557gpio@1d 2nxp,pca9557light-sensor@44default'2isil,isl29023D&i2c@5a820000Z@ s((#peripg /b?n6Tb xdisabled$2fsl,imx8qxp-lpi2cfsl,imx7ulp-lpi2ci2c@5a830000Z@ s))#peripg /c?n6Tc xdisabled$2fsl,imx8qxp-lpi2cfsl,imx7ulp-lpi2cclock-controller@5ac000002fsl,imx8qxp-lpcgZSs`!b i2c0_lpcg_clki2c0_lpcg_ipg_clkT`"clock-controller@5ac100002fsl,imx8qxp-lpcgZSsa!b i2c1_lpcg_clki2c1_lpcg_ipg_clkTa#clock-controller@5ac200002fsl,imx8qxp-lpcgZSsb!b i2c2_lpcg_clki2c2_lpcg_ipg_clkTb(clock-controller@5ac300002fsl,imx8qxp-lpcgZSsc!b i2c3_lpcg_clki2c3_lpcg_ipg_clkTc)bus@5b000000 2simple-bus [[clock-conn-axi 2fixed-clockSCU conn_axi_clk6clock-conn-ahb 2fixed-clockS ! conn_ahb_clkclock-conn-ipg 2fixed-clockS conn_ipg_clk5mmc@5b010000 [s*** #ipgahbperTxokay"2fsl,imx8qxp-usdhcfsl,imx7d-usdhc /? default+mmc@5b020000 [s,,, #ipgahbperTxokay"2fsl,imx8qxp-usdhcfsl,imx7d-usdhc /? default-. !/ */mmc@5b030000 [s000 #ipgahbperT xdisabled"2fsl,imx8qxp-usdhcfsl,imx7d-usdhcethernet@5b040000[0 s111 1#ipgahbenet_clk_refptp/?沀sY@3ETxokay.2fsl,imx8qxp-fecfsl,imx8qm-fecfsl,imx6sx-fecdefault2 Wrgmii-id`3kmdio ethernet-phy@02ethernet-phy-ieee802.3-c223ethernet@5b050000[0 s444 4#ipgahbenet_clk_refptp/?沀sY@3ET xdisabled.2fsl,imx8qxp-fecfsl,imx8qm-fecfsl,imx6sx-fecclock-controller@5b2000002fsl,imx8qxp-lpcg[ Ss56 b9sdhc0_lpcg_per_clksdhc0_lpcg_ipg_clksdhc0_lpcg_ahb_clkT*clock-controller@5b2100002fsl,imx8qxp-lpcg[!Ss56 b9sdhc1_lpcg_per_clksdhc1_lpcg_ipg_clksdhc1_lpcg_ahb_clkT,clock-controller@5b2200002fsl,imx8qxp-lpcg["Ss56 b9sdhc2_lpcg_per_clksdhc2_lpcg_ipg_clksdhc2_lpcg_ahb_clkT0clock-controller@5b2300002fsl,imx8qxp-lpcg[#S0s655b enet0_lpcg_timer_clkenet0_lpcg_txc_sampling_clkenet0_lpcg_ahb_clkenet0_lpcg_rgmii_txc_clkenet0_lpcg_ipg_clkenet0_lpcg_ipg_s_clkT1clock-controller@5b2400002fsl,imx8qxp-lpcg[$S0s655b enet1_lpcg_timer_clkenet1_lpcg_txc_sampling_clkenet1_lpcg_ahb_clkenet1_lpcg_rgmii_txc_clkenet1_lpcg_ipg_clkenet1_lpcg_ipg_s_clkT4bus@5c000000 2simple-bus \\ddr-pmu@5c0200002fsl,imx8-ddr-pmu\ bus@5d000000 2simple-bus ]]clock-lsio-mem 2fixed-clockS  lsio_mem_clkclock-lsio-bus 2fixed-clockS lsio_bus_clk7gpio@5d080000] T 2fsl,imx8qxp-gpiofsl,imx35-gpiogpio@5d090000]  T 2fsl,imx8qxp-gpiofsl,imx35-gpio&gpio@5d0a0000]  T 2fsl,imx8qxp-gpiofsl,imx35-gpiogpio@5d0b0000]  T 2fsl,imx8qxp-gpiofsl,imx35-gpiogpio@5d0c0000]  T 2fsl,imx8qxp-gpiofsl,imx35-gpio/gpio@5d0d0000]  T 2fsl,imx8qxp-gpiofsl,imx35-gpiogpio@5d0e0000] T 2fsl,imx8qxp-gpiofsl,imx35-gpiogpio@5d0f0000] T 2fsl,imx8qxp-gpiofsl,imx35-gpiomailbox@5d1b0000] p xdisabled2fsl,imx8qxp-mufsl,imx6sx-mumailbox@5d1c0000] p-2fsl,imx8-mu-scufsl,imx8qxp-mufsl,imx6sx-mumailbox@5d1d0000] p xdisabled-2fsl,imx8-mu-scufsl,imx8qxp-mufsl,imx6sx-mumailbox@5d1e0000] p xdisabled-2fsl,imx8-mu-scufsl,imx8qxp-mufsl,imx6sx-mumailbox@5d1f0000] p xdisabled-2fsl,imx8-mu-scufsl,imx8qxp-mufsl,imx6sx-mumailbox@5d200000]  pT xdisabled2fsl,imx8qxp-mufsl,imx6sx-mumailbox@5d210000]! pT xdisabled2fsl,imx8qxp-mufsl,imx6sx-mumailbox@5d280000]( pT2fsl,imx8qxp-mufsl,imx6sx-muclock-controller@5d4000002fsl,imx8qxp-lpcg]@S4s7bhpwm0_lpcg_ipg_clkpwm0_lpcg_ipg_hf_clkpwm0_lpcg_ipg_s_clkpwm0_lpcg_ipg_slv_clkpwm0_lpcg_ipg_mstr_clkTclock-controller@5d4100002fsl,imx8qxp-lpcg]AS4s7bhpwm1_lpcg_ipg_clkpwm1_lpcg_ipg_hf_clkpwm1_lpcg_ipg_s_clkpwm1_lpcg_ipg_slv_clkpwm1_lpcg_ipg_mstr_clkTclock-controller@5d4200002fsl,imx8qxp-lpcg]BS4s7bhpwm2_lpcg_ipg_clkpwm2_lpcg_ipg_hf_clkpwm2_lpcg_ipg_s_clkpwm2_lpcg_ipg_slv_clkpwm2_lpcg_ipg_mstr_clkTclock-controller@5d4300002fsl,imx8qxp-lpcg]CS4s7bhpwm3_lpcg_ipg_clkpwm3_lpcg_ipg_hf_clkpwm3_lpcg_ipg_s_clkpwm3_lpcg_ipg_slv_clkpwm3_lpcg_ipg_mstr_clkTclock-controller@5d4400002fsl,imx8qxp-lpcg]DS4s7bhpwm4_lpcg_ipg_clkpwm4_lpcg_ipg_hf_clkpwm4_lpcg_ipg_s_clkpwm4_lpcg_ipg_slv_clkpwm4_lpcg_ipg_mstr_clkTclock-controller@5d4500002fsl,imx8qxp-lpcg]ES4s7bhpwm5_lpcg_ipg_clkpwm5_lpcg_ipg_hf_clkpwm5_lpcg_ipg_s_clkpwm5_lpcg_ipg_slv_clkpwm5_lpcg_ipg_mstr_clkTclock-controller@5d4600002fsl,imx8qxp-lpcg]FS4s7bhpwm6_lpcg_ipg_clkpwm6_lpcg_ipg_hf_clkpwm6_lpcg_ipg_s_clkpwm6_lpcg_ipg_slv_clkpwm6_lpcg_ipg_mstr_clkTclock-controller@5d4700002fsl,imx8qxp-lpcg]GS4s7bhpwm7_lpcg_ipg_clkpwm7_lpcg_ipg_hf_clkpwm7_lpcg_ipg_s_clkpwm7_lpcg_ipg_slv_clkpwm7_lpcg_ipg_mstr_clkTchosen|/bus@5a000000/serial@5a060000memory@80000000memory@usdhc2-vmmc2regulator-fixed SD1_SPWR-- /. interrupt-parent#address-cells#size-cellsmodelcompatibleethernet0ethernet1gpio0gpio1gpio2gpio3gpio4gpio5gpio6gpio7i2c0i2c1i2c2i2c3mmc0mmc1mmc2mu0mu1mu2mu3mu4serial0serial1serial2serial3vpu-core0vpu-core1device_typeregenable-methodi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cacheclocksoperating-points-v2#cooling-cellsphandlecache-levelopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspend#interrupt-cellsinterrupt-controllerinterruptsrangesno-mapmbox-namesmboxes#power-domain-cells#clock-cellsfsl,pinslinux,keycodesstatustimeout-sec#thermal-sensor-cellsclock-frequencyclock-output-namespolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-deviceclock-namesassigned-clocksassigned-clock-ratespower-domainsclock-indices#mbox-cellsmemory-regionpinctrl-namespinctrl-0reset-gpiosgpio-controller#gpio-cellsbus-widthno-sdno-sdionon-removablefsl,tuning-start-tapfsl,tuning-stepvmmc-supplycd-gpioswp-gpiosfsl,num-tx-queuesfsl,num-rx-queuesphy-modephy-handlefsl,magic-packetstdout-pathregulator-nameregulator-min-microvoltregulator-max-microvoltgpioenable-active-high