h8aL(aSedgeble,neural-compute-module-2-ioedgeble,neural-compute-module-2rockchip,rv1126&7Edgeble Neu2 IO Boardaliases=/i2c@ff3f0000B/i2c@ff400000G/i2c@ff520000L/serial@ff560000T/serial@ff410000\/serial@ff570000d/serial@ff580000l/serial@ff590000t/serial@ff5a0000|/mmc@ffc50000cpuscpu@f00cpuarm,cortex-a7pscicpu@f01cpuarm,cortex-a7pscicpu@f02cpuarm,cortex-a7pscicpu@f03cpuarm,cortex-a7psciarm-pmuarm,cortex-a7-pmu0{|}~psci arm,psci-1.0smctimerarm,armv7-timer0   n6display_subsystemrockchip,display-subsystemoscillator fixed-clockn6xin24m*syscon@fe000000&rockchip,rv1126-grfsysconsimple-mfd)syscon@fe020000)rockchip,rv1126-pmugrfsysconsimple-mfdio-domains&rockchip,rv1126-pmu-io-voltage-domain okay " 0 > L Zh v qos@fe860000rockchip,rv1126-qossyscon qos@fe860080rockchip,rv1126-qossyscon qos@fe860200rockchip,rv1126-qossyscon qos@fe86c000rockchip,rv1126-qossyscon qos@fe8a0000rockchip,rv1126-qossyscon qos@fe8a0080rockchip,rv1126-qossyscon qos@fe8a0100rockchip,rv1126-qossyscon qos@fe8a0180rockchip,rv1126-qossyscon interrupt-controller@feff0000 arm,gic-400  @ `   power-management@ff3e0000&rockchip,rv1126-pmusysconsimple-mfd>power-controller!rockchip,rv1126-power-controllerEpower-domain@158ruv power-domain@16opower-domain@10 PZ[i2c@ff3f0000(rockchip,rv1126-i2crockchip,rk3399-i2c?  ! i2cpclkdefault okaypmic@20rockchip,rk809 & rk808-clkout1rk808-clkout2default%3?KWco{ 3regulatorsDCDC_REG1 vdd_npu_vepu ~qregulator-state-mem0DCDC_REG2vdd_arm pqregulator-state-mem0DCDC_REG3vcc_ddrregulator-state-memIDCDC_REG4 vcc3v3_sys2Z2Z regulator-state-memIa2ZDCDC_REG5 vcc_buck5!!regulator-state-memIa!LDO_REG1vcc_0v8 5 5regulator-state-mem0LDO_REG2 vcc1v8_pmuw@w@ regulator-state-memIaw@LDO_REG3 vcc0v8_pmu 5 5regulator-state-memIa 5LDO_REG4vcc_1v8w@w@ regulator-state-memIaw@LDO_REG5 vcc_dovddw@w@regulator-state-mem0LDO_REG6 vcc_dvddOOregulator-state-mem0LDO_REG7 vcc_avdd**regulator-state-mem0LDO_REG8 vccio_sdw@2Z regulator-state-mem0LDO_REG9 vcc3v3_sd2Z2Zregulator-state-mem0SWITCH_REG1vcc_5v0SWITCH_REG2vcc_3v3Ji2c@ff400000(rockchip,rv1126-i2crockchip,rk3399-i2c@  " i2cpclkdefault  disabledserial@ff410000&rockchip,rv1126-uartsnps,dw-apb-uartA n6  baudclkapb_pclk}txrxdefault   disabledpwm@ff430000(rockchip,rv1126-pwmrockchip,rk3328-pwmC pwmpclk#default!  disabledpwm@ff430010(rockchip,rv1126-pwmrockchip,rk3328-pwmC pwmpclk#default"  disabledpwm@ff430020(rockchip,rv1126-pwmrockchip,rk3328-pwmC  pwmpclk#default#  disabledpwm@ff430030(rockchip,rv1126-pwmrockchip,rk3328-pwmC0 pwmpclk#default$  disabledpwm@ff440000(rockchip,rv1126-pwmrockchip,rk3328-pwmD pwmpclk$default%  disabledpwm@ff440010(rockchip,rv1126-pwmrockchip,rk3328-pwmD pwmpclk$default&  disabledpwm@ff440020(rockchip,rv1126-pwmrockchip,rk3328-pwmD  pwmpclk$default'  disabledpwm@ff440030(rockchip,rv1126-pwmrockchip,rk3328-pwmD0 pwmpclk$default(  disabledclock-controller@ff480000rockchip,rv1126-pmucruH)clock-controller@ff490000rockchip,rv1126-cruI*xin24m)dma-controller@ff4e0000arm,pl330arm,primecellN@ apb_pclki2c@ff520000(rockchip,rv1126-i2crockchip,rk3399-i2cR " i2cpclkdefault+  disabledpwm@ff550000(rockchip,rv1126-pwmrockchip,rk3328-pwmU pwmpclk',default  disabledpwm@ff550010(rockchip,rv1126-pwmrockchip,rk3328-pwmU pwmpclk'-default  disabledpwm@ff550020(rockchip,rv1126-pwmrockchip,rk3328-pwmU  pwmpclk'.default  disabledpwm@ff550030(rockchip,rv1126-pwmrockchip,rk3328-pwmU0 pwmpclk'/default okayserial@ff560000&rockchip,rv1126-uartsnps,dw-apb-uartV n6baudclkapb_pclk}txrxdefault 012 okaybluetoothqcom,qca9377-bt3 4default5  serial@ff570000&rockchip,rv1126-uartsnps,dw-apb-uartW n6baudclkapb_pclk} txrxdefault6 okayserial@ff580000&rockchip,rv1126-uartsnps,dw-apb-uartX n6baudclkapb_pclk}  txrxdefault7  disabledserial@ff590000&rockchip,rv1126-uartsnps,dw-apb-uartY n6baudclkapb_pclk}  txrxdefault8  disabledserial@ff5a0000&rockchip,rv1126-uartsnps,dw-apb-uartZ n6 baudclkapb_pclk}txrxdefault9  disabledadc@ff5e0000.rockchip,rv1126-saradcrockchip,rk3399-saradc^ (, saradcapb_pclk ; 'saradc-apb okay3 timer@ff660000,rockchip,rv1126-timerrockchip,rk3288-timerf   - pclktimeri2s@ff800000rockchip,rv1126-i2s-tdm .=Amclk_txmclk_rxhclk}txrxdefault(:;<=>?@ABC cd 'tx-mrx-m)?  disabledvop@ffb00000rockchip,rv1126-vop  ;aclk_vopdclk_vophclk_vop 'axiahbdclk PDWE   disabledportendpoint@0endpoint@1iommu@ffb00f00rockchip,iommu ; aclkifaceeWE   disabledDethernet@ffc40000&rockchip,rv1126-gmacsnps,dwmac-4.20a@_`rmacirqeth_wake_irq)@~Tstmmacethmac_clk_rxmac_clk_txclk_mac_refaclk_macpclk_macclk_mac_speedptp_ref  'stmmacethFGH okay~} sY@}x@inputI&rgmii/JdefaultKLMN:*Cmdiosnps,dwmac-mdioethernet-phy@0ethernet-phy-id001c.c916defaultOLN \ nIstmmac-axi-configzFrx-queues-configGqueue0tx-queues-configHqueue0mmc@ffc500000rockchip,rv1126-dw-mshcrockchip,rk3288-dw-mshc@ N rstbiuciuciu-driveciu-sample WE okaydefault PQRZJ+ mmc@ffc600000rockchip,rv1126-dw-mshcrockchip,rk3288-dw-mshc@ L lmnbiuciuciu-driveciu-sample  okay8J[defaultSTUVZmz+ mmc@ffc700000rockchip,rv1126-dw-mshcrockchip,rk3288-dw-mshc@ M opqbiuciuciu-driveciu-sampleWE okayJWdefault XYZZ + spi@ffc90000 rockchip,sfc@ PvĴclk_sfchclk_sfcvWE okaydefault[flash@0jedec,spi-norpinctrlrockchip,rv1126-pinctrl)gpio@ff460000rockchip,gpio-bankF "& gpio@ff620000rockchip,gpio-bankb #( dgpio@ff630000rockchip,gpio-bankc $) gpio@ff640000rockchip,gpio-bankd %* 4gpio@ff650000rockchip,gpio-banke & + pcfg-pull-up'_pcfg-pull-down4^pcfg-pull-noneC\pcfg-pull-none-drv-level-3CPapcfg-pull-up-drv-level-2'P]pcfg-pull-none-drv-level-0-smtCP_`clk_out_ethernetclk-out-ethernetm1-pinst\Nemmcemmc-bus8t]]]]]]]]Pemmc-clkt]Remmc-cmdt]Qfspifspi-pins`t^_____[i2c0i2c0-xfer t ` `i2c2i2c2-xfer t``i2c3i2c3m0-xfer t\\+i2s0i2s0m0-lrck-txt\=i2s0m0-lrck-rxt\>i2s0m0-mclkt\<i2s0m0-sclk-rxt\;i2s0m0-sclk-txt\:i2s0m0-sdi0t\?i2s0m0-sdo0t\@i2s0m0-sdo1-sdi3t\Ai2s0m0-sdo2-sdi2t\Bi2s0m0-sdo3-sdi1t\Ci2s0m1-lrck-txt\i2s0m1-lrck-rxt \i2s0m1-mclkt\i2s0m1-sclk-rxt \i2s0m1-sclk-txt\i2s0m1-sdi0t\i2s0m1-sdo0t\i2s0m1-sdo1-sdi3t \i2s0m1-sdo2-sdi2t \i2s0m1-sdo3-sdi1t \pwm0pwm0m0-pinst\!pwm1pwm1m0-pinst\"pwm2pwm2m0-pinst\#pwm3pwm3m0-pinst\$pwm4pwm4m0-pinst\%pwm5pwm5m0-pinst\&pwm6pwm6m0-pinst \'pwm7pwm7m0-pinst \(pwm8pwm8m0-pinst\,pwm9pwm9m0-pinst\-pwm10pwm10m0-pinst\.pwm11pwm11m0-pinst\/rgmiirgmiim1-miim t\\Krgmiim1-bus2`t \\ \aaaLrgmiim1-bus4`t\\\aaaMsdmmc0sdmmc0-bus4@t]]]]Usdmmc0-clkt]Ssdmmc0-cmdt ]Tsdmmc0-dett\Vsdmmc1sdmmc1-bus4@t ] ]]]Zsdmmc1-clkt ]Xsdmmc1-cmdt ]Yuart0uart0-xfer t__0uart0-ctsnt\1uart0-rtsnt\2uart1uart1m0-xfer t__ uart2uart2m1-xfer t__6uart3uart3m0-xfer t__7uart4uart4m0-xfer t__8uart5uart5m0-xfer t__9btbt-enablet\5flashflash-vol-selt \bpmicpmic-int-lt _wifiwifi-enable-ht\cetherneteth-phy-rstt^Ovccio-flash-regulatorregulator-fixed  defaultb vccio_flashw@w@J pwrseq-sdiommc-pwrseq-simple3 ext_clockdefaultc ndWchosenserial2:1500000n8vcc12v-dcin-regulatorregulator-fixed vcc12v_dcinevcc5v0-sys-regulatorregulator-fixed vcc5v0_sysLK@LK@ev3v3-sys-regulatorregulator-fixed v3v3_sys2Z2Z #address-cells#size-cellscompatibleinterrupt-parentmodeli2c0i2c2i2c3serial0serial1serial2serial3serial4serial5mmc0device_typeregenable-methodclockscpu-supplyphandleinterruptsinterrupt-affinityclock-frequencyportsclock-output-names#clock-cellsstatuspmuio0-supplypmuio1-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supplyinterrupt-controller#interrupt-cells#power-domain-cellspm_qosrockchip,grfclock-namespinctrl-namespinctrl-0rockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyregulator-nameregulator-always-onregulator-boot-onregulator-initial-moderegulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvoltdmasdma-namesreg-shiftreg-io-width#pwm-cells#reset-cells#dma-cellsarm,pl330-periph-burstenable-gpiosmax-speedvddxo-supplyvddio-supply#io-channel-cellsresetsreset-namesvref-supply#sound-dai-cellsiommuspower-domains#iommu-cellsinterrupt-namessnps,mixed-burstsnps,tsosnps,axi-configsnps,mtl-rx-configsnps,mtl-tx-configassigned-clocksassigned-clock-parentsassigned-clock-ratesclock_in_outphy-handlephy-modephy-supplytx_delayrx_delayreset-assert-usreset-deassert-usreset-gpiossnps,wr_osr_lmtsnps,rd_osr_lmtsnps,blensnps,rx-queues-to-usesnps,tx-queues-to-usefifo-depthmax-frequencybus-widthnon-removablerockchip,default-sample-phasevmmc-supplyvqmmc-supplycap-mmc-highspeedcap-sd-highspeedcard-detect-delaysd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr104cap-sdio-irqkeep-power-in-suspendmmc-pwrseqspi-max-frequencyspi-rx-bus-widthspi-tx-bus-widthrockchip,pmurangesgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsenable-active-highgpiovin-supplystdout-path