8 ( &firefly,roc-rk3328-ccrockchip,rk3328 +7Firefly roc-rk3328-ccaliases=/pinctrl/gpio@ff210000C/pinctrl/gpio@ff220000I/pinctrl/gpio@ff230000O/pinctrl/gpio@ff240000U/serial@ff110000]/serial@ff120000e/serial@ff130000m/i2c@ff150000r/i2c@ff160000w/i2c@ff170000|/i2c@ff180000/ethernet@ff540000/mmc@ff500000/mmc@ff520000cpus+cpu@0cpuarm,cortex-a53xpsci@&3@@R_p{ cpu@1cpuarm,cortex-a53xpsci@&3@@R_p{ cpu@2cpuarm,cortex-a53xpsci@&3@@R_p{ cpu@3cpuarm,cortex-a53xpsci@&3@@R_p{ idle-statespscicpu-sleeparm,idle-statex{l2-cachecache @({opp-table-0operating-points-v2{opp-408000000Q~$@5opp-600000000#F~$@opp-8160000000,B@$@opp-1008000000<$@opp-1200000000G($@opp-1296000000M?d $@analog-soundsimple-audio-cardAi2sZtAnalogokaysimple-audio-card,cpusimple-audio-card,codecarm-pmuarm,cortex-a53-pmu0defg display-subsystemrockchip,display-subsystem hdmi-soundsimple-audio-cardAi2sZtHDMIokaysimple-audio-card,cpusimple-audio-card,codecpsciarm,psci-1.0arm,psci-0.2smctimerarm,armv8-timer0   xin24m fixed-clockn6xin24m{Ei2s@ff000000(rockchip,rk3328-i2srockchip,rk3066-i2s )7i2s_clki2s_hclk  txrx okay{i2s@ff010000(rockchip,rk3328-i2srockchip,rk3066-i2s *8i2s_clki2s_hclktxrx okay{i2s@ff020000(rockchip,rk3328-i2srockchip,rk3066-i2s +9i2s_clki2s_hclktxrx  disabledspdif@ff030000rockchip,rk3328-spdif .: mclkhclk txdefault*  disabledpdm@ff040000 rockchip,pdm=Rpdm_clkpdm_hclkrxdefaultsleep*4 disabledsyscon@ff100000&rockchip,rk3328-grfsysconsimple-mfd{:io-domains"rockchip,rk3328-io-voltage-domainokay>LZhvgpiorockchip,rk3328-grf-gpio{epower-controller!rockchip,rk3328-power-controller+{<power-domain@6power-domain@5 BABpower-domain@8Freboot-modesyscon-reboot-modeRBRBRB RBserial@ff110000&rockchip,rk3328-uartsnps,dw-apb-uart 7&baudclkapb_pclktxrxdefault * !"  disabledserial@ff120000&rockchip,rk3328-uartsnps,dw-apb-uart 8'baudclkapb_pclktxrxdefault *#$%  disabledserial@ff130000&rockchip,rk3328-uartsnps,dw-apb-uart 9(baudclkapb_pclktxrxdefault*& okayi2c@ff150000(rockchip,rk3328-i2crockchip,rk3399-i2c $+7 i2cpclkdefault*' disabledi2c@ff160000(rockchip,rk3328-i2crockchip,rk3399-i2c %+8 i2cpclkdefault*(okaypmic@18rockchip,rk805 )xin32krk805-clkout2default**#DR+^+j+v+{hregulatorsDCDC_REG1 vdd_logic 4 regulator-state-memB@DCDC_REG2vdd_arm 4 {regulator-state-mem~DCDC_REG3vcc_ddrregulator-state-memDCDC_REG4vcc_io2Z2Z{regulator-state-mem2ZLDO_REG1vcc_18w@w@{regulator-state-memw@LDO_REG2 vcc18_emmcw@w@{regulator-state-memw@LDO_REG3vdd_10B@B@regulator-state-memB@i2c@ff170000(rockchip,rk3328-i2crockchip,rk3399-i2c &+9 i2cpclkdefault*, disabledi2c@ff180000(rockchip,rk3328-i2crockchip,rk3399-i2c '+: i2cpclkdefault*- disabledspi@ff190000(rockchip,rk3328-spirockchip,rk3066-spi 1+ spiclkapb_pclk txrxdefault*./01 disabledwatchdog@ff1a0000 rockchip,rk3328-wdtsnps,dw-wdt (pwm@ff1b0000rockchip,rk3328-pwm< pwmpclkdefault*23 disabledpwm@ff1b0010rockchip,rk3328-pwm< pwmpclkdefault*33 disabledpwm@ff1b0020rockchip,rk3328-pwm < pwmpclkdefault*43 disabledpwm@ff1b0030rockchip,rk3328-pwm0< pwmpclkdefault*53 disableddma-controller@ff1f0000arm,pl330arm,primecell@> apb_pclkU{thermal-zonessoc-thermal`v6tripstrip-point0ppassivetrip-point1Lpassive{7soc-crits criticalcooling-mapsmap070 tsadc@ff250000rockchip,rk3328-tsadc% :$P$tsadcapb_pclkinitdefaultsleep*8498 B tsadc-apb :-Dokay{6efuse@ff260000rockchip,rk3328-efuse&P+> pclk_efuseZ id@7cpu-leakage@17logic-leakage@19cpu-version@1an{Fadc@ff280000.rockchip,rk3328-saradcrockchip,rk3399-saradc( Ps%saradcapb_pclk V saradc-apb disabledgpu@ff300000"rockchip,rk3328-maliarm,mali-4500TZW]XY[\"gpgpmmupppp0ppmmu0pp1ppmmu1 buscore fiommu@ff330200rockchip,iommu3 ` aclkiface disablediommu@ff340800rockchip,iommu4@ bF aclkiface disabledvideo-codec@ff350000rockchip,rk3328-vpu5  vdpuF aclkhclk;<iommu@ff350800rockchip,iommu5@  F aclkiface<{;video-codec@ff360000*rockchip,rk3328-vdecrockchip,rk3399-vdec6  BABaxiahbcabaccoreAB ׄׄ=<iommu@ff360480rockchip,iommu 6@6@ JB aclkiface<{=vop@ff370000rockchip,rk3328-vop7>  x;aclk_vopdclk_vophclk_vop  axiahbdclk>okayport+{ endpoint@0?{Diommu@ff373f00rockchip,iommu7?  ; aclkifaceokay{>hdmi@ff3c0000rockchip,rk3328-dw-hdmi< #GFiahbisfrcec@hdmidefault *ABC : okay{ports+port@0endpointD{?port@1codec@ff410000rockchip,rk3328-codecA* pclkmclk : okay{phy@ff430000rockchip,rk3328-hdmi-phyC SEysysclkrefoclkrefpclk hdmi_phyF cpu-versionokay{@clock-controller@ff440000(rockchip,rk3328-crurockchip,crusysconD :x=&'(ABDC"\5H4$ zEEE|n6n6n6ׄn6#FLGрxhxhрxhxh{syscon@ff450000.rockchip,rk3328-usb2phy-grfsysconsimple-mfdE+usb2phy@100rockchip,rk3328-usb2phyEphyclk usb480m_phy{ Gokay{Gotg-port$;<=otg-bvalidotg-idlinestateokay{Vhost-port > linestateokay{Wmmc@ff5000000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcP@   =!JNbiuciuciu-driveciu-sample"-рokay;EWhdefault*HIJKsLmmc@ff5100000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcQ@   >"KObiuciuciu-driveciu-sample"-р disabledmmc@ff5200000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcR@  ?#LPbiuciuciu-driveciu-sample"-рokay;Edefault *MNOethernet@ff540000rockchip,rk3328-gmacT macirq8dWXZYMstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac c stmmaceth :okaydf PPinputQ*rgmiidefault*R3 <)L b'Pw$ethernet@ff550000rockchip,rk3328-gmacU : macirq8TSSUVIstmmacethmac_clk_rxmac_clk_txclk_mac_refaclk_macpclk_macclk_macphy b stmmaceth*rmiiSoutput disabledmdiosnps,dwmac-mdio+ethernet-phy@04ethernet-phy-id1234.d400ethernet-phy-ieee802.3-c22V ddefault*TU{Susb@ff5800002rockchip,rk3328-usbrockchip,rk3066-usbsnps,dwc2X Motghost@ V usb2-phyokayusb@ff5c0000 generic-ehci\  NGWusbokayusb@ff5d0000 generic-ohci]  NGWusbokayusb@ff600000rockchip,rk3328-dwc3snps,dwc3` C`aref_clksuspend_clkbus_clkhost utmi_wide  + M n okayinterrupt-controller@ff811000 arm,gic-400  @ @ `   {crypto@ff060000rockchip,rk3328-crypto@ PQ;hclk_masterhclk_slavesclk D crypto-rstpinctrlrockchip,rk3328-pinctrl :+ gpio@ff210000rockchip,gpio-bank! 3  {cgpio@ff220000rockchip,gpio-bank" 4  {)gpio@ff230000rockchip,gpio-bank# 5  gpio@ff240000rockchip,gpio-bank$ 6  pcfg-pull-up {Zpcfg-pull-down {bpcfg-pull-none {Xpcfg-pull-none-2ma  {apcfg-pull-up-2ma  pcfg-pull-up-4ma  {[pcfg-pull-none-4ma  {^pcfg-pull-down-4ma  pcfg-pull-none-8ma  {\pcfg-pull-up-8ma  {]pcfg-pull-none-12ma  {_pcfg-pull-up-12ma  {`pcfg-output-high pcfg-output-low pcfg-input-high  {Ypcfg-input i2c0i2c0-xfer )XX{'i2c1i2c1-xfer )XX{(i2c2i2c2-xfer ) XX{,i2c3i2c3-xfer )XX{-i2c3-pins )XXhdmi_i2chdmii2c-xfer )XX{Bpdm-0pdmm0-clk )X{pdmm0-fsync )Xpdmm0-sdi0 )X{pdmm0-sdi1 )X{pdmm0-sdi2 )X{pdmm0-sdi3 )X{pdmm0-clk-sleep )Y{pdmm0-sdi0-sleep )Y{pdmm0-sdi1-sleep )Y{pdmm0-sdi2-sleep )Y{pdmm0-sdi3-sleep )Y{pdmm0-fsync-sleep )Ytsadcotp-pin ) X{8otp-out ) X{9uart0uart0-xfer ) XZ{ uart0-cts ) X{!uart0-rts ) X{"uart0-rts-pin ) Xuart1uart1-xfer )XZ{#uart1-cts )X{$uart1-rts )X{%uart1-rts-pin )Xuart2-0uart2m0-xfer )XZuart2-1uart2m1-xfer )XZ{&spi0-0spi0m0-clk )Zspi0m0-cs0 ) Zspi0m0-tx ) Zspi0m0-rx ) Zspi0m0-cs1 ) Zspi0-1spi0m1-clk )Zspi0m1-cs0 )Zspi0m1-tx )Zspi0m1-rx )Zspi0m1-cs1 )Zspi0-2spi0m2-clk )Z{.spi0m2-cs0 )Z{1spi0m2-tx )Z{/spi0m2-rx )Z{0i2s1i2s1-mclk )Xi2s1-sclk )Xi2s1-lrckrx )Xi2s1-lrcktx )Xi2s1-sdi )Xi2s1-sdo )Xi2s1-sdio1 )Xi2s1-sdio2 )Xi2s1-sdio3 )Xi2s1-sleep )YYYYYYYYYi2s2-0i2s2m0-mclk )Xi2s2m0-sclk )Xi2s2m0-lrckrx )Xi2s2m0-lrcktx )Xi2s2m0-sdi )Xi2s2m0-sdo )Xi2s2m0-sleep` )YYYYYYi2s2-1i2s2m1-mclk )Xi2s2m1-sclk )Xi2sm1-lrckrx )Xi2s2m1-lrcktx )Xi2s2m1-sdi )Xi2s2m1-sdo )Xi2s2m1-sleepP )YYYYYspdif-0spdifm0-tx )Xspdif-1spdifm1-tx )Xspdif-2spdifm2-tx )X{sdmmc0-0sdmmc0m0-pwren )[sdmmc0m0-pin )[sdmmc0-1sdmmc0m1-pwren )[sdmmc0m1-pin )[{dsdmmc0sdmmc0-clk )\{Hsdmmc0-cmd )]{Isdmmc0-dectn )[{Jsdmmc0-wrprt )[sdmmc0-bus1 )]sdmmc0-bus4@ )]]]]{Ksdmmc0-pins )[[[[[[[[sdmmc0extsdmmc0ext-clk )^sdmmc0ext-cmd )[sdmmc0ext-wrprt )[sdmmc0ext-dectn )[sdmmc0ext-bus1 )[sdmmc0ext-bus4@ )[[[[sdmmc0ext-pins )[[[[[[[[sdmmc1sdmmc1-clk ) \sdmmc1-cmd ) ]sdmmc1-pwren )]sdmmc1-wrprt )]sdmmc1-dectn )]sdmmc1-bus1 )]sdmmc1-bus4@ )]]]]sdmmc1-pins ) [ [[[[[[[[emmcemmc-clk )_{Memmc-cmd )`{Nemmc-pwren )Xemmc-rstnout )Xemmc-bus1 )`emmc-bus4@ )````emmc-bus8 )````````{Opwm0pwm0-pin )X{2pwm1pwm1-pin )X{3pwm2pwm2-pin )X{4pwmirpwmir-pin )X{5gmac-1rgmiim1-pins` ) \ ^^\^^^ ^ ^\ \^^\\\ \^\\\\{Rrmiim1-pins )a_aaaa a a_ _ X XXXXXgmac2phyfephyled-speed10 )Xfephyled-duplex )Xfephyled-rxm1 )X{Tfephyled-txm1 )Xfephyled-linkm1 )X{Utsadc_pintsadc-int ) Xtsadc-pin ) Xhdmi_pinhdmi-cec )X{Ahdmi-hpd )b{Ccif-0dvp-d2d9-m0 )XXXXX X X XXXXXcif-1dvp-d2d9-m1 )XXXXXXXXXXXXpmicpmic-int-l )Z{*usb2usb20-host-drv )X{fchosen 7serial2:1500000n8external-gmac-clock fixed-clocksY@ gmac_clkin{Pdc-12vregulator-fixeddc_12v{gsdmmc-regulatorregulator-fixed Gcdefault*dvcc_sd2Z2Z C{Lsdmmcio-regulatorregulator-gpio New@2Z vcc_sdio Tvoltagew@2Z C+{vcc-host1-5v-regulatorregulator-fixed c G)default*f vcc_host1_5v C+vcc-sysregulator-fixedvcc_sysLK@LK@ Cg{+vcc-phy-regulatorregulator-fixedvcc_phy{Qleds gpio-ledsled-0 vfirefly:blue:power |heartbeat Nh onled-1 vfirefly:yellow:user |mmc1 Nh off compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3serial0serial1serial2i2c0i2c1i2c2i2c3ethernet0mmc0mmc1device_typeregclocks#cooling-cellscpu-idle-statesdynamic-power-coefficientenable-methodoperating-points-v2i-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachecpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendsimple-audio-card,formatsimple-audio-card,mclk-fssimple-audio-card,namestatussound-daiinterruptsinterrupt-affinityports#clock-cellsclock-frequencyclock-output-namesclock-namesdmasdma-names#sound-dai-cellspinctrl-namespinctrl-0pinctrl-1vccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplypmuio-supplygpio-controller#gpio-cells#power-domain-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loaderreg-io-widthreg-shiftrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-onregulator-on-in-suspendregulator-suspend-microvolt#pwm-cellsarm,pl330-periph-burst#dma-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontributionassigned-clocksassigned-clock-ratespinctrl-2resetsreset-namesrockchip,grfrockchip,hw-tshut-temp#thermal-sensor-cellsrockchip,efuse-sizebits#io-channel-cellsinterrupt-names#iommu-cellsiommuspower-domainsremote-endpointphysphy-namesnvmem-cellsnvmem-cell-names#phy-cells#reset-cellsassigned-clock-parentsfifo-depthmax-frequencybus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpsd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplymmc-ddr-1_8vmmc-hs200-1_8vnon-removabletx-fifo-depthrx-fifo-depthsnps,txpblclock_in_outphy-supplyphy-modesnps,aalsnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ussnps,rxpbltx_delayrx_delayphy-handlephy-is-integrateddr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephy_typesnps,dis-del-phy-power-chg-quirksnps,dis_enblslpm_quirksnps,dis-tx-ipgap-linecheck-quirksnps,dis-u2-freeclk-exists-quirksnps,dis_u2_susphy_quirksnps,dis_u3_susphy_quirk#interrupt-cellsinterrupt-controllerrangesbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathvin-supplygpiosregulator-typeenable-active-highlabellinux,default-triggerdefault-state