F8L(Dcompulab,omap3-sbc-t3517compulab,omap3-cm-t3517ti,am3517ti,omap3 +!7CompuLab SBC-T3517 with CM-T3517chosenaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/serial@4806a000T/ocp@68000000/serial@4806c000\/ocp@68000000/serial@49020000d/ocp@68000000/serial@4809e000l/ocp@68000000/can@5c050000p/dvi-connectory/svideo-connectorcpus+cpu@0arm,cortex-a8cpucpupmu@54000000arm,cortex-a8-pmuTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2iva disableddsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-bush +l3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-bus + pinmux@30 ti,omap3-padconfpinctrl-single08+ )FdefaultTpinmux_uart3_pins^nprpinmux_mmc1_pins0^rpinmux_green_led_pins^rpinmux_dss_dpi_pins_common^rpinmux_dss_dpi_pins_cm_t35x0^rpinmux_ads7846_pins^rpinmux_mcspi1_pins ^rpinmux_i2c1_pins^rpinmux_mcbsp2_pins ^ rpinmux_hsusb1_phy_reset_pins^Hrpinmux_hsusb2_phy_reset_pins^Jrpinmux_otg_drv_vbus^rpinmux_mmc2_pins0^(*,.02rpinmux_wl12xx_core_pins^Frpinmux_usb_hub_pins^Trpinmux_smsc2_pins^rpinmux_tfp410_pins^rpinmux_i2c3_pins^rpinmux_sb_t35_audio_amp^rpinmux_mmc1_aux_pins^Drpinmux_sb_t35_usb_hub_pins^rscm_conf@270sysconsimple-busp0+ p0rpbias_regulator@2b0ti,pbias-omap3ti,pbias-omapzpbias_mmc_omap2430pbias_mmc_omap2430w@-rclocks+mcbsp5_mux_fck@68ti,composite-mux-clockhr mcbsp5_fckti,composite-clock rmcbsp1_mux_fck@4ti,composite-mux-clockr mcbsp1_fckti,composite-clock rmcbsp2_mux_fck@4ti,composite-mux-clock rmcbsp2_fckti,composite-clock rmcbsp3_mux_fck@68ti,composite-mux-clock hrmcbsp3_fckti,composite-clockrmcbsp4_mux_fck@68ti,composite-mux-clock hrmcbsp4_fckti,composite-clockremac_ick@32cti,am35xx-gate-clock,rzemac_fck@32cti,gate-clock, rvpfe_ick@32cti,am35xx-gate-clock,r{vpfe_fck@32cti,gate-clock, hsotgusb_ick_am35xx@32cti,am35xx-gate-clock,r|hsotgusb_fck_am35xx@32cti,gate-clock,r}hecc_ck@32cti,am35xx-gate-clock,r~clockdomainspinmux@a00 ti,omap3-padconfpinctrl-single \+ )pinmux_wl12xx_wkup_pins^raes@480c5000 ti,omap3-aesaesH PPABtxrxprm@48306000 ti,omap3-prmH0`@ clocks+virt_16_8m_ck fixed-clockYrosc_sys_ck@d40 ti,mux-clock @rsys_ck@1270ti,divider-clockprsys_clkout1@d70ti,gate-clock pdpll3_x2_ckfixed-factor-clock&dpll3_m2x2_ckfixed-factor-clock &r"dpll4_x2_ckfixed-factor-clock!&corex2_fckfixed-factor-clock"&r#wkup_l4_ickfixed-factor-clock&rRcorex2_d3_fckfixed-factor-clock#&rscorex2_d5_fckfixed-factor-clock#&rtclockdomainscm@48004000 ti,omap3-cmH@@clocks+dummy_apb_pclk fixed-clockomap_32k_fck fixed-clockrDvirt_12m_ck fixed-clockrvirt_13m_ck fixed-clock]@rvirt_19200000_ck fixed-clock$rvirt_26000000_ck fixed-clockrvirt_38_4m_ck fixed-clockIrdpll4_ck@d00ti,omap3-dpll-per-clock D 0r!dpll4_m2_ck@d48ti,divider-clock!? Hr$dpll4_m2x2_mul_ckfixed-factor-clock$&r%dpll4_m2x2_ck@d00ti,gate-clock% 0r&omap_96m_alwon_fckfixed-factor-clock&&r-dpll3_ck@d00ti,omap3-dpll-core-clock @ 0rdpll3_m3_ck@1140ti,divider-clock@r'dpll3_m3x2_mul_ckfixed-factor-clock'&r(dpll3_m3x2_ck@d00ti,gate-clock(  0r)emu_core_alwon_ckfixed-factor-clock)&rfsys_altclk fixed-clockr2mcbsp_clks fixed-clockrdpll3_m2_ck@d40ti,divider-clock @r core_ckfixed-factor-clock &r*dpll1_fck@940ti,divider-clock* @r+dpll1_ck@904ti,omap3-dpll-clock+  $ @ 4rdpll1_x2_ckfixed-factor-clock&r,dpll1_x2m2_ck@944ti,divider-clock, Dr@cm_96m_fckfixed-factor-clock-&r.omap_96m_fck@d40 ti,mux-clock. @rIdpll4_m3_ck@e40ti,divider-clock! @r/dpll4_m3x2_mul_ckfixed-factor-clock/&r0dpll4_m3x2_ck@d00ti,gate-clock0 0r1omap_54m_fck@d40 ti,mux-clock12 @r<cm_96m_d2_fckfixed-factor-clock.&r3omap_48m_fck@d40 ti,mux-clock32 @r4omap_12m_fckfixed-factor-clock4&rKdpll4_m4_ck@e40ti,divider-clock! @r5dpll4_m4x2_mul_ckti,fixed-factor-clock5FTar6dpll4_m4x2_ck@d00ti,gate-clock6 0arxdpll4_m5_ck@f40ti,divider-clock!?@r7dpll4_m5x2_mul_ckti,fixed-factor-clock7FTar8dpll4_m5x2_ck@d00ti,gate-clock8 0adpll4_m6_ck@1140ti,divider-clock!?@r9dpll4_m6x2_mul_ckfixed-factor-clock9&r:dpll4_m6x2_ck@d00ti,gate-clock: 0r;emu_per_alwon_ckfixed-factor-clock;&rgclkout2_src_gate_ck@d70 ti,composite-no-wait-gate-clock* pr=clkout2_src_mux_ck@d70ti,composite-mux-clock*.< pr>clkout2_src_ckti,composite-clock=>r?sys_clkout2@d70ti,divider-clock?@ ptmpu_ckfixed-factor-clock@&rAarm_fck@924ti,divider-clockA $emu_mpu_alwon_ckfixed-factor-clockA&rhl3_ick@a40ti,divider-clock* @rBl4_ick@a40ti,divider-clockB @rCrm_ick@c40ti,divider-clockC @gpt10_gate_fck@a00ti,composite-gate-clock  rEgpt10_mux_fck@a40ti,composite-mux-clockD @rFgpt10_fckti,composite-clockEFgpt11_gate_fck@a00ti,composite-gate-clock  rGgpt11_mux_fck@a40ti,composite-mux-clockD @rHgpt11_fckti,composite-clockGHcore_96m_fckfixed-factor-clockI&rmmchs2_fck@a00ti,wait-gate-clock rmmchs1_fck@a00ti,wait-gate-clock ri2c3_fck@a00ti,wait-gate-clock ri2c2_fck@a00ti,wait-gate-clock ri2c1_fck@a00ti,wait-gate-clock rmcbsp5_gate_fck@a00ti,composite-gate-clock  rmcbsp1_gate_fck@a00ti,composite-gate-clock  r core_48m_fckfixed-factor-clock4&rJmcspi4_fck@a00ti,wait-gate-clockJ rmcspi3_fck@a00ti,wait-gate-clockJ rmcspi2_fck@a00ti,wait-gate-clockJ rmcspi1_fck@a00ti,wait-gate-clockJ ruart2_fck@a00ti,wait-gate-clockJ ruart1_fck@a00ti,wait-gate-clockJ  rcore_12m_fckfixed-factor-clockK&rLhdq_fck@a00ti,wait-gate-clockL rcore_l3_ickfixed-factor-clockB&rMsdrc_ick@a10ti,wait-gate-clockM rygpmc_fckfixed-factor-clockM&core_l4_ickfixed-factor-clockC&rNmmchs2_ick@a10ti,omap3-interface-clockN rmmchs1_ick@a10ti,omap3-interface-clockN rhdq_ick@a10ti,omap3-interface-clockN rmcspi4_ick@a10ti,omap3-interface-clockN rmcspi3_ick@a10ti,omap3-interface-clockN rmcspi2_ick@a10ti,omap3-interface-clockN rmcspi1_ick@a10ti,omap3-interface-clockN ri2c3_ick@a10ti,omap3-interface-clockN ri2c2_ick@a10ti,omap3-interface-clockN ri2c1_ick@a10ti,omap3-interface-clockN ruart2_ick@a10ti,omap3-interface-clockN ruart1_ick@a10ti,omap3-interface-clockN  rgpt11_ick@a10ti,omap3-interface-clockN  rgpt10_ick@a10ti,omap3-interface-clockN  rmcbsp5_ick@a10ti,omap3-interface-clockN  rmcbsp1_ick@a10ti,omap3-interface-clockN  romapctrl_ick@a10ti,omap3-interface-clockN rdss_tv_fck@e00ti,gate-clock<rdss_96m_fck@e00ti,gate-clockIrdss2_alwon_fck@e00ti,gate-clockrdummy_ck fixed-clockgpt1_gate_fck@c00ti,composite-gate-clock rOgpt1_mux_fck@c40ti,composite-mux-clockD @rPgpt1_fckti,composite-clockOPaes2_ick@a10ti,omap3-interface-clockN rwkup_32k_fckfixed-factor-clockD&rQgpio1_dbck@c00ti,gate-clockQ rsha12_ick@a10ti,omap3-interface-clockN rwdt2_fck@c00ti,wait-gate-clockQ rwdt2_ick@c10ti,omap3-interface-clockR rwdt1_ick@c10ti,omap3-interface-clockR rgpio1_ick@c10ti,omap3-interface-clockR romap_32ksync_ick@c10ti,omap3-interface-clockR rgpt12_ick@c10ti,omap3-interface-clockR rgpt1_ick@c10ti,omap3-interface-clockR rper_96m_fckfixed-factor-clock-&r per_48m_fckfixed-factor-clock4&rSuart3_fck@1000ti,wait-gate-clockS rgpt2_gate_fck@1000ti,composite-gate-clockrTgpt2_mux_fck@1040ti,composite-mux-clockD@rUgpt2_fckti,composite-clockTUgpt3_gate_fck@1000ti,composite-gate-clockrVgpt3_mux_fck@1040ti,composite-mux-clockD@rWgpt3_fckti,composite-clockVWgpt4_gate_fck@1000ti,composite-gate-clockrXgpt4_mux_fck@1040ti,composite-mux-clockD@rYgpt4_fckti,composite-clockXYgpt5_gate_fck@1000ti,composite-gate-clockrZgpt5_mux_fck@1040ti,composite-mux-clockD@r[gpt5_fckti,composite-clockZ[gpt6_gate_fck@1000ti,composite-gate-clockr\gpt6_mux_fck@1040ti,composite-mux-clockD@r]gpt6_fckti,composite-clock\]gpt7_gate_fck@1000ti,composite-gate-clockr^gpt7_mux_fck@1040ti,composite-mux-clockD@r_gpt7_fckti,composite-clock^_gpt8_gate_fck@1000ti,composite-gate-clock r`gpt8_mux_fck@1040ti,composite-mux-clockD@ragpt8_fckti,composite-clock`agpt9_gate_fck@1000ti,composite-gate-clock rbgpt9_mux_fck@1040ti,composite-mux-clockD@rcgpt9_fckti,composite-clockbcper_32k_alwon_fckfixed-factor-clockD&rdgpio6_dbck@1000ti,gate-clockdrgpio5_dbck@1000ti,gate-clockdrgpio4_dbck@1000ti,gate-clockdrgpio3_dbck@1000ti,gate-clockdrgpio2_dbck@1000ti,gate-clockd rwdt3_fck@1000ti,wait-gate-clockd rper_l4_ickfixed-factor-clockC&regpio6_ick@1010ti,omap3-interface-clockergpio5_ick@1010ti,omap3-interface-clockergpio4_ick@1010ti,omap3-interface-clockergpio3_ick@1010ti,omap3-interface-clockergpio2_ick@1010ti,omap3-interface-clocke rwdt3_ick@1010ti,omap3-interface-clocke ruart3_ick@1010ti,omap3-interface-clocke ruart4_ick@1010ti,omap3-interface-clockergpt9_ick@1010ti,omap3-interface-clocke rgpt8_ick@1010ti,omap3-interface-clocke rgpt7_ick@1010ti,omap3-interface-clockergpt6_ick@1010ti,omap3-interface-clockergpt5_ick@1010ti,omap3-interface-clockergpt4_ick@1010ti,omap3-interface-clockergpt3_ick@1010ti,omap3-interface-clockergpt2_ick@1010ti,omap3-interface-clockermcbsp2_ick@1010ti,omap3-interface-clockermcbsp3_ick@1010ti,omap3-interface-clockermcbsp4_ick@1010ti,omap3-interface-clockermcbsp2_gate_fck@1000ti,composite-gate-clockr mcbsp3_gate_fck@1000ti,composite-gate-clockrmcbsp4_gate_fck@1000ti,composite-gate-clockremu_src_mux_ck@1140 ti,mux-clockfgh@riemu_src_ckti,clkdm-gate-clockirjpclk_fck@1140ti,divider-clockj@pclkx2_fck@1140ti,divider-clockj@atclk_fck@1140ti,divider-clockj@traceclk_src_fck@1140 ti,mux-clockfgh@rktraceclk_fck@1140ti,divider-clockk @secure_32k_fck fixed-clockrlgpt12_fckfixed-factor-clockl&wdt1_fckfixed-factor-clockl&ipss_ick@a10ti,am35xx-interface-clockM rrmii_ck fixed-clockrpclk_ck fixed-clockruart4_ick_am35xx@a10ti,omap3-interface-clockN uart4_fck_am35xx@a00ti,wait-gate-clockJ dpll5_ck@d04ti,omap3-dpll-clock  $ L 4rmdpll5_m2_ck@d50ti,divider-clockm Prwsgx_gate_fck@b00ti,composite-gate-clock* rucore_d3_ckfixed-factor-clock*&rncore_d4_ckfixed-factor-clock*&rocore_d6_ckfixed-factor-clock*&rpomap_192m_alwon_fckfixed-factor-clock&&rqcore_d2_ckfixed-factor-clock*&rrsgx_mux_fck@b40ti,composite-mux-clock nop.qrst @rvsgx_fckti,composite-clockuvsgx_ick@b10ti,wait-gate-clockB rcpefuse_fck@a08ti,gate-clock rts_fck@a08ti,gate-clockD rusbtll_fck@a08ti,wait-gate-clockw rusbtll_ick@a18ti,omap3-interface-clockN rmmchs3_ick@a10ti,omap3-interface-clockN rmmchs3_fck@a00ti,wait-gate-clock rdss1_alwon_fck_3430es2@e00ti,dss-gate-clockxardss_ick_3430es2@e10ti,omap3-dss-interface-clockCrusbhost_120m_fck@1400ti,gate-clockwrusbhost_48m_fck@1400ti,dss-gate-clock4rusbhost_ick@1410ti,omap3-dss-interface-clockCrclockdomainscore_l3_clkdmti,clockdomainyz{|}~dpll3_clkdmti,clockdomaindpll1_clkdmti,clockdomainper_clkdmti,clockdomainhemu_clkdmti,clockdomainjdpll4_clkdmti,clockdomain!wkup_clkdmti,clockdomain dss_clkdmti,clockdomaincore_l4_clkdmti,clockdomaindpll5_clkdmti,clockdomainmsgx_clkdmti,clockdomainusbhost_clkdmti,clockdomain counter@48320000ti,omap-counter32kH2  counter_32kinterrupt-controller@48200000ti,omap3-intcH rdma-controller@48056000"ti,omap3630-sdmati,omap3430-sdmaH`  `dmargpio@48310000ti,omap3-gpioH1gpio1rgpio@49050000ti,omap3-gpioIgpio2rgpio@49052000ti,omap3-gpioI gpio3rgpio@49054000ti,omap3-gpioI@ gpio4gpio@49056000ti,omap3-gpioI`!gpio5rgpio@49058000ti,omap3-gpioI"gpio6rserial@4806a000ti,omap3-uartH H12txrxuart1lserial@4806c000ti,omap3-uartHI34txrxuart2lserial@49020000ti,omap3-uartIJ56txrxuart3lFdefaultTi2c@48070000 ti,omap3-i2cH8txrx+i2c1FdefaultTat24@50 atmel,24c02 Pi2c@48072000 ti,omap3-i2cH 9txrx+i2c2i2c@48060000 ti,omap3-i2cH=txrx+i2c3FdefaultTat24@50 atmel,24c02 Pmailbox@48094000ti,omap3-mailboxmailboxH @ 2 disableddsp D Ospi@48098000ti,omap2-mcspiH A+mcspi1Z@#$%&'()* tx0rx0tx1rx1tx2rx2tx3rx3FdefaultTads7846@0FdefaultT ti,ads7846hs`   spi@4809a000ti,omap2-mcspiH B+mcspi2Z +,-.tx0rx0tx1rx1spi@480b8000ti,omap2-mcspiH [+mcspi3Z tx0rx0tx1rx1spi@480ba000ti,omap2-mcspiH 0+mcspi4ZFGtx0rx01w@480b2000 ti,omap3-1wH :hdq1wmmc@4809c000ti,omap3-hsmmcH Smmc1=>txrx!FdefaultT.8 D Mmmc@480b4000ti,omap3-hsmmcH @Vmmc2/0txrxFdefaultT8Vc.q+wlcore@2 ti,wl1271 Immc@480ad000ti,omap3-hsmmcH ^mmc3MNtxrx disabledmmu@480bd400ti,omap2-iommuH mmu_isp disabledmmu@5d000000ti,omap2-iommu]mmu_iva disabledwdt@48314000 ti,omap3-wdtH1@ wd_timer2mcbsp@48074000ti,omap3-mcbspH@mpu ;< commontxrxmcbsp1 txrxfck disabledmcbsp@49022000ti,omap3-mcbspI I mpusidetone>?commontxrxsidetonemcbsp2mcbsp2_sidetone!"txrxfckickokFdefaultTmcbsp@49024000ti,omap3-mcbspI@I mpusidetoneYZcommontxrxsidetonemcbsp3mcbsp3_sidetonetxrxfckick disabledmcbsp@49026000ti,omap3-mcbspI`mpu 67 commontxrxmcbsp4txrxfck disabledmcbsp@48096000ti,omap3-mcbspH `mpu QR commontxrxmcbsp5txrxfck disabledsham@480c3000ti,omap3-shamshamH 0d1Erxtimer@48318000ti,omap3430-timerH1%timer1timer@49032000ti,omap3430-timerI &timer2timer@49034000ti,omap3430-timerI@'timer3timer@49036000ti,omap3430-timerI`(timer4timer@49038000ti,omap3430-timerI)timer5timer@4903a000ti,omap3430-timerI*timer6timer@4903c000ti,omap3430-timerI+timer7timer@4903e000ti,omap3430-timerI,timer8 timer@49040000ti,omap3430-timerI-timer9 timer@48086000ti,omap3430-timerH`.timer10 timer@48088000ti,omap3430-timerH/timer11 timer@48304000ti,omap3430-timerH0@_timer12usbhstll@48062000 ti,usbhs-tllH N usb_tll_hsusbhshost@48064000ti,usbhs-hostH@ usb_host_hs+ (ehci-phy 3ehci-phyohci@48064400ti,ohci-omap3HDL>ehci@48064800 ti,ehci-omapHHMVgpmc@6e000000ti,omap3430-gpmcgpmcnrxtx[g+ -rnand@0,0ti,omap2-nand  yswxxxxZ.<ZKeHt<xxZ+partition@0xloaderpartition@80000ubootpartition@260000uboot environment&partition@2a0000linux*@partition@6a0000rootfsjethernet@4,0smsc,lan9221smsc,lan9115FdefaultT  (.-<-exKKtK6Neuusb_otg_hs@480ab000ti,omap3-musbH \]mcdma usb_otg_hs  disableddss@48050000 ti,omap3-dssHok dss_corefck+FdefaultTdispc@48050400ti,omap3-dispcH dss_dispcfckencoder@4804fc00 ti,omap3-dsiHH@H protophypll disabled dss_dsi1 fcksys_clkencoder@48050800ti,omap3-rfbiH disabled dss_rfbifckickencoder@48050c00ti,omap3-vencH ok dss_vencfckportendpointrportendpointrssi-controller@48058000 ti,omap3-ssissi disabledHHsysgddGgdd_mpu+ssi-port@4805a000ti,omap3-ssi-portHHtxrxCDssi-port@4805b000ti,omap3-ssi-portHHtxrxEFam35x_otg_hs@5c040000ti,omap3-musb am35x_otg_hsokay\GmcFdefaultTethernet@5c000000ti,am3517-emac davinci_emacokay\CDEFz#> Wjzickethernet@5c030000ti,davinci_mdio davinci_mdiookay\|B@+fckserial@4809e000ti,omap3-uartuart4 disabledH T76txrxlpinmux@480025d8 ti,omap3-padconfpinctrl-singleH%$+ )can@5c050000ti,am3517-hecc disabled\\0\ hecchecc-rammbx~memory@80000000memoryleds gpio-ledsFdefaultTledb cm-t3x:green G heartbeathsusb1_power_regregulator-fixed hsusb1_vbus2Z2Zprhsusb2_power_regregulator-fixed hsusb2_vbus2Z2Zprhsusb1_phyusb-nop-xceivhFdefaultT rhsusb2_phyusb-nop-xceivhFdefaultT rads7846-regregulator-fixed ads7846-reg2Z2Zrsvideo-connectorsvideo-connectortvportendpointrregulator-vmmcregulator-fixedvmmc2Z2Zrwl12xx_vmmc2regulator-fixedvw1271FdefaultTw@w@ N rwl12xx_vaux2regulator-fixedvwl1271_vaux2w@w@rencoder ti,tfp410 FdefaultTports+port@0endpointrport@1endpointrdvi-connectordvi-connectordviportendpointraudio_ampregulator-fixed audio_ampFdefaultT regulator-vddvario-sb-t35regulator-fixed vddvariorregulator-vdd33a-sb-t35regulator-fixedvdd33ar compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2serial0serial1serial2serial3candisplay0display1device_typeregclocksclock-namesclock-latencyinterruptsti,hwmodsstatusranges#pinctrl-cells#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0pinctrl-single,pinsphandlesysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lock#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedpagesize#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csvcc-supplyspi-max-frequencypendown-gpioti,x-minti,x-maxti,y-minti,y-maxti,x-plate-ohmsti,pressure-maxti,debounce-maxti,debounce-tolti,debounce-repwakeup-sourceti,dual-voltpbias-supplybus-widthvmmc-supplywp-gpioscd-gpiosvqmmc-supplynon-removablecap-power-off-cardref-clock-frequency#iommu-cellsti,#tlb-entriesreg-namesinterrupt-namesti,buffer-size#sound-dai-cellsti,timer-alwonti,timer-dspti,timer-pwmti,timer-secureport1-modeport2-moderemote-wakeup-connectedphysgpmc,num-csgpmc,num-waitpinsnand-bus-widthgpmc,device-widthti,nand-ecc-optgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,we-on-nsgpmc,we-off-nsgpmc,oe-on-nsgpmc,oe-off-nsgpmc,page-burst-access-nsgpmc,access-nsgpmc,cycle2cycle-delay-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,wr-access-nsgpmc,wr-data-mux-bus-nslabelbank-widthgpmc,cycle2cycle-samecsengpmc,cycle2cycle-diffcsengpmc,bus-turnaround-nsgpmc,wait-monitoring-nsgpmc,clk-activation-nsvddvario-supplyvdd33a-supplyreg-io-widthsmsc,save-mac-addressmultipointnum-epsram-bitsremote-endpointti,channelsdata-linesti,davinci-ctrl-reg-offsetti,davinci-ctrl-mod-reg-offsetti,davinci-ctrl-ram-offsetti,davinci-ctrl-ram-sizeti,davinci-rmii-enlocal-mac-addressbus_freqlinux,default-triggerstartup-delay-us#phy-cellsreset-gpiosenable-active-highpowerdown-gpiosregulator-always-on