8( ?Ҙ!ti,am3517-evmti,am3517ti,omap3 +&7TI AM3517 EVM (AM3517/05 TMDSEVM3517)chosenaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/serial@4806a000T/ocp@68000000/serial@4806c000\/ocp@68000000/serial@49020000d/ocp@68000000/serial@4809e000l/ocp@68000000/can@5c050000 p/display@0cpus+cpu@0arm,cortex-a8ycpucpupmu@54000000arm,cortex-a8-pmuTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2iva disableddsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-bush +l3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-bus + pinmux@30 ti,omap3-padconfpinctrl-single08+,IdefaultWpinmux_wl12xx_buffer_pinsa&upinmux_mmc2_pinsXa(*,.02468:upinmux_rtc_pinsaupinmux_tsc2004_pinsaupinmux_uart2_pins(aDFHJupinmux_leds_pinsa$&upinmux_mmc1_pins@a "upinmux_pwm_pinsaupinmux_backlight_pinsaupinmux_dss_dpi_pinsaupinmux_hsusb1_rst_pinsauscm_conf@270sysconsimple-busp0+ p0upbias_regulator@2b0ti,pbias-omap3ti,pbias-omap}pbias_mmc_omap2430pbias_mmc_omap2430w@-uclocks+mcbsp5_mux_fck@68ti,composite-mux-clockhu mcbsp5_fckti,composite-clock umcbsp1_mux_fck@4ti,composite-mux-clocku mcbsp1_fckti,composite-clock umcbsp2_mux_fck@4ti,composite-mux-clock umcbsp2_fckti,composite-clock umcbsp3_mux_fck@68ti,composite-mux-clock humcbsp3_fckti,composite-clockumcbsp4_mux_fck@68ti,composite-mux-clock humcbsp4_fckti,composite-clockuemac_ick@32cti,am35xx-gate-clock,uzemac_fck@32cti,gate-clock, uvpfe_ick@32cti,am35xx-gate-clock,u{vpfe_fck@32cti,gate-clock, hsotgusb_ick_am35xx@32cti,am35xx-gate-clock,u|hsotgusb_fck_am35xx@32cti,gate-clock,u}hecc_ck@32cti,am35xx-gate-clock,u~clockdomainspinmux@a00 ti,omap3-padconfpinctrl-single \+,pinmux_wl12xx_wkup_pinsa uaes@480c5000 ti,omap3-aesaesH PPABtxrxprm@48306000 ti,omap3-prmH0`@ clocks+virt_16_8m_ck fixed-clockYuosc_sys_ck@d40 ti,mux-clock @usys_ck@1270ti,divider-clockpusys_clkout1@d70ti,gate-clock pdpll3_x2_ckfixed-factor-clock)dpll3_m2x2_ckfixed-factor-clock )u"dpll4_x2_ckfixed-factor-clock!)corex2_fckfixed-factor-clock")u#wkup_l4_ickfixed-factor-clock)uRcorex2_d3_fckfixed-factor-clock#)uscorex2_d5_fckfixed-factor-clock#)utclockdomainscm@48004000 ti,omap3-cmH@@clocks+dummy_apb_pclk fixed-clockomap_32k_fck fixed-clockuDvirt_12m_ck fixed-clockuvirt_13m_ck fixed-clock]@uvirt_19200000_ck fixed-clock$uvirt_26000000_ck fixed-clockuvirt_38_4m_ck fixed-clockIudpll4_ck@d00ti,omap3-dpll-per-clock D 0u!dpll4_m2_ck@d48ti,divider-clock!? Hu$dpll4_m2x2_mul_ckfixed-factor-clock$)u%dpll4_m2x2_ck@d00ti,gate-clock% 3u&omap_96m_alwon_fckfixed-factor-clock&)u-dpll3_ck@d00ti,omap3-dpll-core-clock @ 0udpll3_m3_ck@1140ti,divider-clock@u'dpll3_m3x2_mul_ckfixed-factor-clock')u(dpll3_m3x2_ck@d00ti,gate-clock(  3u)emu_core_alwon_ckfixed-factor-clock))ufsys_altclk fixed-clocku2mcbsp_clks fixed-clockudpll3_m2_ck@d40ti,divider-clock @u core_ckfixed-factor-clock )u*dpll1_fck@940ti,divider-clock* @u+dpll1_ck@904ti,omap3-dpll-clock+  $ @ 4udpll1_x2_ckfixed-factor-clock)u,dpll1_x2m2_ck@944ti,divider-clock, Du@cm_96m_fckfixed-factor-clock-)u.omap_96m_fck@d40 ti,mux-clock. @uIdpll4_m3_ck@e40ti,divider-clock! @u/dpll4_m3x2_mul_ckfixed-factor-clock/)u0dpll4_m3x2_ck@d00ti,gate-clock0 3u1omap_54m_fck@d40 ti,mux-clock12 @u<cm_96m_d2_fckfixed-factor-clock.)u3omap_48m_fck@d40 ti,mux-clock32 @u4omap_12m_fckfixed-factor-clock4)uKdpll4_m4_ck@e40ti,divider-clock! @u5dpll4_m4x2_mul_ckti,fixed-factor-clock5IWdu6dpll4_m4x2_ck@d00ti,gate-clock6 3duxdpll4_m5_ck@f40ti,divider-clock!?@u7dpll4_m5x2_mul_ckti,fixed-factor-clock7IWdu8dpll4_m5x2_ck@d00ti,gate-clock8 3ddpll4_m6_ck@1140ti,divider-clock!?@u9dpll4_m6x2_mul_ckfixed-factor-clock9)u:dpll4_m6x2_ck@d00ti,gate-clock: 3u;emu_per_alwon_ckfixed-factor-clock;)ugclkout2_src_gate_ck@d70 ti,composite-no-wait-gate-clock* pu=clkout2_src_mux_ck@d70ti,composite-mux-clock*.< pu>clkout2_src_ckti,composite-clock=>u?sys_clkout2@d70ti,divider-clock?@ pwmpu_ckfixed-factor-clock@)uAarm_fck@924ti,divider-clockA $emu_mpu_alwon_ckfixed-factor-clockA)uhl3_ick@a40ti,divider-clock* @uBl4_ick@a40ti,divider-clockB @uCrm_ick@c40ti,divider-clockC @gpt10_gate_fck@a00ti,composite-gate-clock  uEgpt10_mux_fck@a40ti,composite-mux-clockD @uFgpt10_fckti,composite-clockEFgpt11_gate_fck@a00ti,composite-gate-clock  uGgpt11_mux_fck@a40ti,composite-mux-clockD @uHgpt11_fckti,composite-clockGHcore_96m_fckfixed-factor-clockI)ummchs2_fck@a00ti,wait-gate-clock ummchs1_fck@a00ti,wait-gate-clock ui2c3_fck@a00ti,wait-gate-clock ui2c2_fck@a00ti,wait-gate-clock ui2c1_fck@a00ti,wait-gate-clock umcbsp5_gate_fck@a00ti,composite-gate-clock  umcbsp1_gate_fck@a00ti,composite-gate-clock  u core_48m_fckfixed-factor-clock4)uJmcspi4_fck@a00ti,wait-gate-clockJ umcspi3_fck@a00ti,wait-gate-clockJ umcspi2_fck@a00ti,wait-gate-clockJ umcspi1_fck@a00ti,wait-gate-clockJ uuart2_fck@a00ti,wait-gate-clockJ uuart1_fck@a00ti,wait-gate-clockJ  ucore_12m_fckfixed-factor-clockK)uLhdq_fck@a00ti,wait-gate-clockL ucore_l3_ickfixed-factor-clockB)uMsdrc_ick@a10ti,wait-gate-clockM uygpmc_fckfixed-factor-clockM)core_l4_ickfixed-factor-clockC)uNmmchs2_ick@a10ti,omap3-interface-clockN ummchs1_ick@a10ti,omap3-interface-clockN uhdq_ick@a10ti,omap3-interface-clockN umcspi4_ick@a10ti,omap3-interface-clockN umcspi3_ick@a10ti,omap3-interface-clockN umcspi2_ick@a10ti,omap3-interface-clockN umcspi1_ick@a10ti,omap3-interface-clockN ui2c3_ick@a10ti,omap3-interface-clockN ui2c2_ick@a10ti,omap3-interface-clockN ui2c1_ick@a10ti,omap3-interface-clockN uuart2_ick@a10ti,omap3-interface-clockN uuart1_ick@a10ti,omap3-interface-clockN  ugpt11_ick@a10ti,omap3-interface-clockN  ugpt10_ick@a10ti,omap3-interface-clockN  umcbsp5_ick@a10ti,omap3-interface-clockN  umcbsp1_ick@a10ti,omap3-interface-clockN  uomapctrl_ick@a10ti,omap3-interface-clockN udss_tv_fck@e00ti,gate-clock<udss_96m_fck@e00ti,gate-clockIudss2_alwon_fck@e00ti,gate-clockudummy_ck fixed-clockgpt1_gate_fck@c00ti,composite-gate-clock uOgpt1_mux_fck@c40ti,composite-mux-clockD @uPgpt1_fckti,composite-clockOPaes2_ick@a10ti,omap3-interface-clockN uwkup_32k_fckfixed-factor-clockD)uQgpio1_dbck@c00ti,gate-clockQ usha12_ick@a10ti,omap3-interface-clockN uwdt2_fck@c00ti,wait-gate-clockQ uwdt2_ick@c10ti,omap3-interface-clockR uwdt1_ick@c10ti,omap3-interface-clockR ugpio1_ick@c10ti,omap3-interface-clockR uomap_32ksync_ick@c10ti,omap3-interface-clockR ugpt12_ick@c10ti,omap3-interface-clockR ugpt1_ick@c10ti,omap3-interface-clockR uper_96m_fckfixed-factor-clock-)u per_48m_fckfixed-factor-clock4)uSuart3_fck@1000ti,wait-gate-clockS ugpt2_gate_fck@1000ti,composite-gate-clockuTgpt2_mux_fck@1040ti,composite-mux-clockD@uUgpt2_fckti,composite-clockTUgpt3_gate_fck@1000ti,composite-gate-clockuVgpt3_mux_fck@1040ti,composite-mux-clockD@uWgpt3_fckti,composite-clockVWgpt4_gate_fck@1000ti,composite-gate-clockuXgpt4_mux_fck@1040ti,composite-mux-clockD@uYgpt4_fckti,composite-clockXYgpt5_gate_fck@1000ti,composite-gate-clockuZgpt5_mux_fck@1040ti,composite-mux-clockD@u[gpt5_fckti,composite-clockZ[gpt6_gate_fck@1000ti,composite-gate-clocku\gpt6_mux_fck@1040ti,composite-mux-clockD@u]gpt6_fckti,composite-clock\]gpt7_gate_fck@1000ti,composite-gate-clocku^gpt7_mux_fck@1040ti,composite-mux-clockD@u_gpt7_fckti,composite-clock^_gpt8_gate_fck@1000ti,composite-gate-clock u`gpt8_mux_fck@1040ti,composite-mux-clockD@uagpt8_fckti,composite-clock`agpt9_gate_fck@1000ti,composite-gate-clock ubgpt9_mux_fck@1040ti,composite-mux-clockD@ucgpt9_fckti,composite-clockbcper_32k_alwon_fckfixed-factor-clockD)udgpio6_dbck@1000ti,gate-clockdugpio5_dbck@1000ti,gate-clockdugpio4_dbck@1000ti,gate-clockdugpio3_dbck@1000ti,gate-clockdugpio2_dbck@1000ti,gate-clockd uwdt3_fck@1000ti,wait-gate-clockd uper_l4_ickfixed-factor-clockC)uegpio6_ick@1010ti,omap3-interface-clockeugpio5_ick@1010ti,omap3-interface-clockeugpio4_ick@1010ti,omap3-interface-clockeugpio3_ick@1010ti,omap3-interface-clockeugpio2_ick@1010ti,omap3-interface-clocke uwdt3_ick@1010ti,omap3-interface-clocke uuart3_ick@1010ti,omap3-interface-clocke uuart4_ick@1010ti,omap3-interface-clockeugpt9_ick@1010ti,omap3-interface-clocke ugpt8_ick@1010ti,omap3-interface-clocke ugpt7_ick@1010ti,omap3-interface-clockeugpt6_ick@1010ti,omap3-interface-clockeugpt5_ick@1010ti,omap3-interface-clockeugpt4_ick@1010ti,omap3-interface-clockeugpt3_ick@1010ti,omap3-interface-clockeugpt2_ick@1010ti,omap3-interface-clockeumcbsp2_ick@1010ti,omap3-interface-clockeumcbsp3_ick@1010ti,omap3-interface-clockeumcbsp4_ick@1010ti,omap3-interface-clockeumcbsp2_gate_fck@1000ti,composite-gate-clocku mcbsp3_gate_fck@1000ti,composite-gate-clockumcbsp4_gate_fck@1000ti,composite-gate-clockuemu_src_mux_ck@1140 ti,mux-clockfgh@uiemu_src_ckti,clkdm-gate-clockiujpclk_fck@1140ti,divider-clockj@pclkx2_fck@1140ti,divider-clockj@atclk_fck@1140ti,divider-clockj@traceclk_src_fck@1140 ti,mux-clockfgh@uktraceclk_fck@1140ti,divider-clockk @secure_32k_fck fixed-clockulgpt12_fckfixed-factor-clockl)wdt1_fckfixed-factor-clockl)ipss_ick@a10ti,am35xx-interface-clockM urmii_ck fixed-clockupclk_ck fixed-clockuuart4_ick_am35xx@a10ti,omap3-interface-clockN uart4_fck_am35xx@a00ti,wait-gate-clockJ dpll5_ck@d04ti,omap3-dpll-clock  $ L 4umdpll5_m2_ck@d50ti,divider-clockm Puwsgx_gate_fck@b00ti,composite-gate-clock* uucore_d3_ckfixed-factor-clock*)uncore_d4_ckfixed-factor-clock*)uocore_d6_ckfixed-factor-clock*)upomap_192m_alwon_fckfixed-factor-clock&)uqcore_d2_ckfixed-factor-clock*)ursgx_mux_fck@b40ti,composite-mux-clock nop.qrst @uvsgx_fckti,composite-clockuvsgx_ick@b10ti,wait-gate-clockB ucpefuse_fck@a08ti,gate-clock uts_fck@a08ti,gate-clockD uusbtll_fck@a08ti,wait-gate-clockw uusbtll_ick@a18ti,omap3-interface-clockN ummchs3_ick@a10ti,omap3-interface-clockN ummchs3_fck@a00ti,wait-gate-clock udss1_alwon_fck_3430es2@e00ti,dss-gate-clockxdudss_ick_3430es2@e10ti,omap3-dss-interface-clockCuusbhost_120m_fck@1400ti,gate-clockwuusbhost_48m_fck@1400ti,dss-gate-clock4uusbhost_ick@1410ti,omap3-dss-interface-clockCuclockdomainscore_l3_clkdmti,clockdomainyz{|}~dpll3_clkdmti,clockdomaindpll1_clkdmti,clockdomainper_clkdmti,clockdomainhemu_clkdmti,clockdomainjdpll4_clkdmti,clockdomain!wkup_clkdmti,clockdomain dss_clkdmti,clockdomaincore_l4_clkdmti,clockdomaindpll5_clkdmti,clockdomainmsgx_clkdmti,clockdomainusbhost_clkdmti,clockdomain counter@48320000ti,omap-counter32kH2  counter_32kinterrupt-controller@48200000ti,omap3-intcH udma-controller@48056000"ti,omap3630-sdmati,omap3430-sdmaH`  `dmaugpio@48310000ti,omap3-gpioH1gpio1ugpio@49050000ti,omap3-gpioIgpio2ugpio@49052000ti,omap3-gpioI gpio3ugpio@49054000ti,omap3-gpioI@ gpio4ugpio@49056000ti,omap3-gpioI`!gpio5ugpio@49058000ti,omap3-gpioI"gpio6userial@4806a000ti,omap3-uartH H12txrxuart1lserial@4806c000ti,omap3-uartHI34txrxuart2lIdefaultWbluetooth ti,wl1271-st -serial@49020000ti,omap3-uartIJ56txrxuart3li2c@48070000 ti,omap3-i2cH8txrx+i2c1s35390a@30 sii,s35390a0IdefaultW tps65023@48 ti,tps65023HregulatorsVDCDC1 vdd_core%OOuVDCDC2vdd_io%2Z2ZuVDCDC3vdd_1v8%w@w@uLDO1 vdd_usb18%w@w@LDO2 vdd_usb33%2Z2Ztsc2004@4b ti,tsc2004K9IdefaultW DWj@i2c@48072000 ti,omap3-i2cH 9txrx+i2c2gpio@21 ti,tca6416!ui2c@48060000 ti,omap3-i2cH=txrx+i2c3mailbox@48094000ti,omap3-mailboxmailboxH @ disableddsp ) 4spi@48098000ti,omap2-mcspiH A+mcspi1?@#$%&'()* tx0rx0tx1rx1tx2rx2tx3rx3spi@4809a000ti,omap2-mcspiH B+mcspi2? +,-.tx0rx0tx1rx1spi@480b8000ti,omap2-mcspiH [+mcspi3? tx0rx0tx1rx1spi@480ba000ti,omap2-mcspiH 0+mcspi4?FGtx0rx01w@480b2000 ti,omap3-1wH :hdq1wmmc@4809c000ti,omap3-hsmmcH Smmc1M=>txrxZokayIdefaultWgs } mmc@480b4000ti,omap3-hsmmcH @Vmmc2/0txrxVokayIdefaultWgs+wlcore@2 ti,wl1271  mmc@480ad000ti,omap3-hsmmcH ^mmc3MNtxrx disabledmmu@480bd400ti,omap2-iommuH mmu_isp disabledmmu@5d000000ti,omap2-iommu]mmu_iva disabledwdt@48314000 ti,omap3-wdtH1@ wd_timer2mcbsp@48074000ti,omap3-mcbspH@mpu ;< commontxrxmcbsp1 txrxfck disabledmcbsp@49022000ti,omap3-mcbspI I mpusidetone>?commontxrxsidetonemcbsp2mcbsp2_sidetone!"txrxfckick disabledmcbsp@49024000ti,omap3-mcbspI@I mpusidetoneYZcommontxrxsidetonemcbsp3mcbsp3_sidetonetxrxfckick disabledmcbsp@49026000ti,omap3-mcbspI`mpu 67 commontxrxmcbsp4txrxfck disabledmcbsp@48096000ti,omap3-mcbspH `mpu QR commontxrxmcbsp5txrxfck disabledsham@480c3000ti,omap3-shamshamH 0d1Erxtimer@48318000ti,omap3430-timerH1%timer10timer@49032000ti,omap3430-timerI &timer2timer@49034000ti,omap3430-timerI@'timer3timer@49036000ti,omap3430-timerI`(timer4timer@49038000ti,omap3430-timerI)timer5?timer@4903a000ti,omap3430-timerI*timer6?timer@4903c000ti,omap3430-timerI+timer7?timer@4903e000ti,omap3430-timerI,timer8L?timer@49040000ti,omap3430-timerI-timer9Ltimer@48086000ti,omap3430-timerH`.timer10Ltimer@48088000ti,omap3430-timerH/timer11Lutimer@48304000ti,omap3430-timerH0@_timer120Yusbhstll@48062000 ti,usbhs-tllH N usb_tll_hsusbhshost@48064000ti,usbhs-hostH@ usb_host_hs+ iehci-phyohci@48064400ti,ohci-omap3HDLtehci@48064800 ti,ehci-omapHHMgpmc@6e000000ti,omap3430-gpmcgpmcnrxtx+0nand@0,0ti,omap2-nandmicron,mt29f4g16abchch bch8,, /"B,U(d6s@RR(+usb_otg_hs@480ab000ti,omap3-musbH \]mcdma usb_otg_hs  disableddss@48050000 ti,omap3-dssHok dss_corefck+IdefaultW dispc@48050400ti,omap3-dispcH dss_dispcfckencoder@4804fc00 ti,omap3-dsiHH@H protophypll disabled dss_dsi1 fcksys_clkencoder@48050800ti,omap3-rfbiH disabled dss_rfbifckickencoder@48050c00ti,omap3-vencH  disabled dss_vencfckportendpoint.ussi-controller@48058000 ti,omap3-ssissi disabledHHsysgddGgdd_mpu+ssi-port@4805a000ti,omap3-ssi-portHHtxrxCDssi-port@4805b000ti,omap3-ssi-portHHtxrxEFam35x_otg_hs@5c040000ti,omap3-musb am35x_otg_hs disabled\Gmcethernet@5c000000ti,am3517-emac davinci_emacokay\CDEF}9Ts zickethernet@5c030000ti,davinci_mdio davinci_mdiookay\B@+fckserial@4809e000ti,omap3-uartuart4 disabledH T76txrxlpinmux@480025d8 ti,omap3-padconfpinctrl-singleH%$+,IdefaultWpinmux_hsusb1_pins`a  ucan@5c050000ti,am3517-hecc disabled\\0\ hecchecc-rammbx~wl12xx_bufregulator-fixed wl1271_bufw@w@IdefaultW %uwl12xx_vmmc2regulator-fixedvwl1271w@w@IdefaultW p%umemory@80000000ymemoryvmmcregulator-fixed vmmc_fixed2Z2Zugpio-keysgpio-keys-polled duser_pbUser Push Button user_sw_1User Switch 1 user_sw_2User Switch 2  user_sw_3User Switch 3  user_sw_4User Switch 4  user_sw_5User Switch 5  user_sw_6User Switch 6  user_sw_7User Switch 7 user_sw_8User Switch 8 gpio-leds gpio-ledsIdefaultWuser_led_1am3517evm:green:user_led_1 (onuser_led_2am3517evm:green:user_led_2 (onuser_led_3am3517evm:green:user_led_3  6mmc0user_led_4am3517evm:green:user_led_4  6heartbeatdisplay@0 panel-dpi15okayIdefault portendpointupanel-timingT@LT\iu* backlightpwm-backlightIdefaultWLK@, (2<FPZd dmtimer-pwm@11ti,omap-dmtimer-pwmIdefaultW  uhsusb1_phyusb-nop-xceiv ( 4u compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2serial0serial1serial2serial3candisplay0device_typeregclocksclock-namesclock-latencycpu0-supplyinterruptsti,hwmodsstatusranges#pinctrl-cells#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0pinctrl-single,pinsphandlesysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lock#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedenable-gpiosmax-speedregulator-always-onvio-supplytouchscreen-fuzz-xtouchscreen-fuzz-ytouchscreen-fuzz-pressuretouchscreen-size-xtouchscreen-size-ytouchscreen-max-pressureti,x-plate-ohmsti,esd-recovery-timeout-msvcc-supply#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csti,dual-voltpbias-supplyvmmc-supplybus-widthwp-gpioscd-gpiosnon-removablecap-power-off-cardref-clock-frequencytcxo-clock-frequency#iommu-cellsti,#tlb-entriesreg-namesinterrupt-namesti,buffer-size#sound-dai-cellsti,timer-alwonti,timer-dspti,timer-pwmti,timer-secureport1-moderemote-wakeup-connectedphysgpmc,num-csgpmc,num-waitpinslinux,mtd-namenand-bus-widthti,nand-ecc-optgpmc,sync-clk-psgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,we-off-nsgpmc,oe-off-nsgpmc,access-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,wr-access-nsgpmc,wr-data-mux-bus-nsgpmc,device-widthmultipointnum-epsram-bitsvdds_dsi-supplyvdda_video-supplyremote-endpointdata-linesti,davinci-ctrl-reg-offsetti,davinci-ctrl-mod-reg-offsetti,davinci-ctrl-ram-offsetti,davinci-ctrl-ram-sizeti,davinci-rmii-enlocal-mac-addressbus_freqgpiovin-supplystartup-delay-usenable-active-highpoll-intervallabellinux,codedefault-statelinux,default-triggerhactivevactivehfront-porchhback-porchhsync-lenvback-porchvfront-porchvsync-lenhsync-activevsync-activede-activepixelclk-activepower-supplypwmsbrightness-levelsdefault-brightness-levelti,timers#pwm-cellsreset-gpios#phy-cells