� ��6�82\('2$$rockchip,rk3036-evbrockchip,rk3036&!7Rockchip RK3036 Evaluation boardaliases=/i2c@20072000B/i2c@20056000G/i2c@2005a000L/mmc@1021c000R/mmc@10214000X/mmc@10218000^/serial@20060000f/serial@20064000n/serial@20068000v/spi@20074000cpuszrockchip,rk3036-smpcpu@f00�cpuarm,cortex-a7��� s�B@��@��cpu@f01�cpuarm,cortex-a7���bus simple-bus�pdma@20078000arm,pl330arm,primecell� �@����� apb_pclk� arm-pmuarm,cortex-a7-pmu�LM(display-subsystemrockchip,display-subsystem;timerarm,armv7-timerA0�   en6oscillator fixed-clocken6uxin24m��sram@10080000 mmio-sram�  � smp-sram@0rockchip,rk3066-smp-sram�gpu@10090000"rockchip,rk3036-maliarm,mali-400� 0��gpgpmmupp0ppmmu0�@����@@ buscore�x �disabledvop@10118000rockchip,rk3036-vop��� �+��d�aclk_vopdclk_vophclk_vop�uvw �axiahbdclk� �disabledport�endpoint@0���iommu@10118300rockchip,iommu�� �+�vop_mmu��� aclkiface� �disabled�interrupt-controller@10139000 arm,gic-400 ��� � �  � �usb@101800002rockchip,rk3036-usbrockchip,rk3066-usbsnps,dwc2� � ��otg'otg/AP��@@  �disabledusb@101c00002rockchip,rk3036-usbrockchip,rk3066-usbsnps,dwc2� � ��otg'host �disabledethernet@10200000#rockchip,rk3036-emacsnps,arc-emac� @ �_����hclkmacrefmacclk��l�d�rmii�okay�default� �  � � ethernet-phy@0�� mmc@102140000rockchip,rk3036-dw-mshcrockchip,rk3288-dw-mshc�!@@e<4`�<4`��Dbiuciu� ��Q�reset �disabledmmc@102180000rockchip,rk3036-dw-mshcrockchip,rk3288-dw-mshc�!�@�<4` ��Eswbiuciuciu-driveciu-sample� ��R�reset �disabledmmc@1021c0000rockchip,rk3036-dw-mshcrockchip,rk3288-dw-mshc�!�@ ���e<4`�<4` ��Guybiuciuciu-driveciu-sample �(3 8rx-tx�BO�default ��S�reset �disabledi2s@10220000(rockchip,rk3036-i2srockchip,rk3066-i2s�"@ �3i2s_clki2s_hclk�R�3 8txrx�default�] �disabledclock-controller@20000000rockchip,rk3036-cru� _�n��#g���syscon@20008000&rockchip,rk3036-grfsysconsimple-mfd� ��reboot-modesyscon-reboot-mode{��RB��RB��RB� �RB�acodec-ana@20030000 rk3036-codec� @_ acodec_pclk�q �disabledhdmi@20034000rockchip,rk3036-inno-hdmi� @@ �-�hpclk_�default� �disabledportendpoint@0���timer@20044000,rockchip,rk3036-timerrockchip,rk3288-timer� @  � �a timerpclkpwm@20050000(rockchip,rk3036-pwmrockchip,rk2928-pwm� ��^pwm�default� �disabledpwm@20050010(rockchip,rk3036-pwmrockchip,rk2928-pwm� ��^pwm�default� �disabledpwm@20050020(rockchip,rk3036-pwmrockchip,rk2928-pwm�  ��^pwm�default� �disabledpwm@20050030(rockchip,rk3036-pwmrockchip,rk2928-pwm� 0��^pwm�default� �disabledi2c@20056000(rockchip,rk3036-i2crockchip,rk3288-i2c� ` �i2c�M�default��okayhym8563@51haoyu,hym8563�Q�e�uxin32ki2c@2005a000(rockchip,rk3036-i2crockchip,rk3288-i2c� � �i2c�N�default� �disabledserial@20060000&rockchip,rk3036-uartsnps,dw-apb-uart�  ���en6�MUbaudclkapb_pclk�default � �disabledserial@20064000&rockchip,rk3036-uartsnps,dw-apb-uart� @ ���en6�NVbaudclkapb_pclk�default� �disabledserial@20068000&rockchip,rk3036-uartsnps,dw-apb-uart� � ���en6�OWbaudclkapb_pclk�default��okayi2c@20072000(rockchip,rk3036-i2crockchip,rk3288-i2c�   �i2c�L�default�  �disabledspi@20074000rockchip,rockchip-spi� @ ��RAapb-pclkspi_pclk3  8txrx�default�!"#$ �disabledpinctrlrockchip,rk3036-pinctrl_�gpio0@2007c000rockchip,gpio-bank� � �$�@��gpio1@20080000rockchip,gpio-bank�  �%�A��gpio2@20084000rockchip,gpio-bank� @ �&�B��� pcfg_pull_default��&pcfg-pull-none �%pwm0pwm0-pin%�pwm1pwm1-pin%�pwm2pwm2-pin%�pwm3pwm3-pin%�sdmmcsdmmc-clk%sdmmc-cmd&sdmmc-cd&sdmmc-bus1&sdmmc-bus4@&&&&sdiosdio-bus1 &sdio-bus4@ & & &&sdio-cmd&sdio-clk %emmcemmc-clk%�emmc-cmd&�emmc-bus8�&&&&&&&&�emacemac-xfer� & &&&&&&&� emac-mdio  &&� i2c0i2c0-xfer %%� i2c1i2c1-xfer %%�i2c2i2c2-xfer %%�i2si2s-bus`&&&&&&�hdmihdmi-ctl@% % % %�uart0uart0-xfer &%�uart0-cts&�uart0-rts%�uart1uart1-xfer &%�uart2uart2-xfer &%�spi-pinsspi-txd&�!spi-rxd&�"spi-clk&�#spi-cs0&�$spi-cs1&memory@60000000�memory�`@ #address-cells#size-cellscompatibleinterrupt-parentmodeli2c0i2c1i2c2mshc0mshc1mshc2serial0serial1serial2spienable-methoddevice_typeregresetsoperating-pointsclock-latencyclocksphandlerangesinterrupts#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstclock-namesinterrupt-affinityportsarm,cpu-registers-not-fw-configuredclock-frequencyclock-output-names#clock-cellsinterrupt-namesassigned-clocksassigned-clock-ratesstatusreset-namesiommusremote-endpoint#iommu-cellsinterrupt-controller#interrupt-cellsdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizerockchip,grfassigned-clock-parentsmax-speedphy-modepinctrl-namespinctrl-0phyphy-reset-gpiosphy-reset-durationmax-frequencyfifo-depthbus-widthcap-mmc-highspeedrockchip,default-sample-phasedisable-wpdmasdma-namesmmc-ddr-1_8vnon-removable#sound-dai-cells#reset-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loader#pwm-cellsreg-shiftreg-io-widthgpio-controller#gpio-cellsbias-pull-pin-defaultbias-disablerockchip,pins