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#address-cells#size-cellsmodelcompatiblegpio0gpio1serial0serial1interrupts-extendedcontrollerinterrupt-parentpcie-mem-aperturepcie-io-aperturerangesregclocksstatuscache-unifiedcache-levelarm,double-linefill-incrarm,double-linefill-wraparm,double-linefillprefetch-datainterrupts#interrupt-cellsinterrupt-controllerphandlepinctrl-namespinctrl-0labelreg-shiftreg-io-widthmarvell,pinsmarvell,functionreg-namesngpiosgpio-controller#gpio-cells#pwm-cells#clock-cells#phy-cellsmsi-controllerclock-namestx-csum-limitphy-modebuffer-managerbm,pool-longbm,pool-shortspeedfull-duplexdmacap,memcpydmacap,xordmacap,memsetethernetmarvell,crypto-sramsmarvell,crypto-sram-sizeinternal-memclock-output-namesnand-rbmarvell,nand-keep-confignand-on-flash-bbtread-onlymrvl,clk-delay-cyclesusb-phyno-memory-wccell-indexdevice_typemsi-parentbus-rangeassigned-addressesinterrupt-map-maskinterrupt-mapmarvell,pcie-portmarvell,pcie-laneclock-frequencyenable-methodstdout-pathvcc-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltenable-active-highgpiolinux,codedefault-statelinux,default-trigger