8{d({,'rockchip,rk3288-fennecrockchip,rk3288&7Rockchip RK3288 Fennec Boardchosenaliases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff140000Q/i2c@ff660000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/dwmmc@ff0f0000k/dwmmc@ff0c0000q/dwmmc@ff0d0000w/dwmmc@ff0e0000}/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000memorymemoryarm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500cpuarm,cortex-a12`@p@ @OOa sB@ ~ ' 9  K 0 $@29EKcpu@501cpuarm,cortex-a12EKcpu@502cpuarm,cortex-a12EKcpu@503cpuarm,cortex-a12EKamba simple-busSdma-controller@ff250000arm,pl330arm,primecell%@Ze2 apb_pclkEKdma-controller@ff600000arm,pl330arm,primecell`@Ze2 apb_pclk disableddma-controller@ffb20000arm,pl330arm,primecell@Ze2 apb_pclkECKCreserved-memorySdma-unusable@fe000000oscillator fixed-clockn6xin24mE K timerarm,armv7-timer0   n6timer@ff810000rockchip,rk3288-timer  H 2 a timerpclkdisplay-subsystemrockchip,display-subsystem dwmmc@ff0c0000rockchip,rk3288-dw-mshcр 2Drvbiuciuciu-driveciu-sample  @ disableddwmmc@ff0d0000rockchip,rk3288-dw-mshcр 2Eswbiuciuciu-driveciu-sample ! @ disableddwmmc@ff0e0000rockchip,rk3288-dw-mshcр 2Ftxbiuciuciu-driveciu-sample "@ disableddwmmc@ff0f0000rockchip,rk3288-dw-mshcр 2Guybiuciuciu-driveciu-sample #@okay",>IWadefaulto saradc@ff100000rockchip,saradc $y2I[saradcapb_pclkW saradc-apb disabledspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spi2ARspiclkapb_pclk  txrx ,adefaulto disabledspi@ff120000(rockchip,rk3288-spirockchip,rk3066-spi2BSspiclkapb_pclk txrx -adefaulto disabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spi2CTspiclkapb_pclktxrx .adefaulto disabledi2c@ff140000rockchip,rk3288-i2c >i2c2Madefaulto disabledi2c@ff150000rockchip,rk3288-i2c ?i2c2Oadefaulto disabledi2c@ff160000rockchip,rk3288-i2c @i2c2Padefaulto disabledi2c@ff170000rockchip,rk3288-i2c Ai2c2Qadefaulto  disabledserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart 72MUbaudclkapb_pclkadefaulto! disabledserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart 82NVbaudclkapb_pclkadefaulto" disabledserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uarti 92OWbaudclkapb_pclkadefaulto#okayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart :2PXbaudclkapb_pclkadefaulto$ disabledserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart ;2QYbaudclkapb_pclkadefaulto% disabledthermal-zonesreserve_thermal&cpu_thermald&tripscpu_alert0ppassiveE'K'cpu_alert1$passiveE(K(cpu_crit_ criticalcooling-mapsmap0'  map1(  gpu_thermald&tripsgpu_alert0ppassiveE)K)gpu_crit_ criticalcooling-mapsmap0)  tsadc@ff280000rockchip,rk3288-tsadc( %2HZtsadcapb_pclk tsadc-apbainitdefaultsleepo*+&*0Fs disabledE&K&ethernet@ff290000rockchip,rk3288-gmac)]macirqeth_wake_irqm,82fgc]Mstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macB stmmacethokayz-inputadefaulto./012rgmii 'B@ 30usb@ff500000 generic-ehciP 2usbhost4usbokayusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2T 2otghost5 usb2-phyokayusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2X 2otgotg&8G@@ V6 usb2-phyokayusb@ff5c0000 generic-ehci\ 2usbhostokayi2c@ff650000rockchip,rk3288-i2ce <i2c2Ladefaulto7okaypmic@1brockchip,rk808&8xin32krk808-clkout2adefaulto9:`;;;;;;<<<< <<regulatorsDCDC_REG1#7I qapyvdd_armEKregulator-state-memDCDC_REG2#7I Payvdd_gpuregulator-state-memB@DCDC_REG3#7yvcc_ddrregulator-state-memDCDC_REG4#7I2Za2Zyvcc_ioE<K<regulator-state-mem2ZLDO_REG1#7I2Za2Z yvccio_pmuregulator-state-mem2ZLDO_REG2#7I2Za2Zyvcca_33regulator-state-memLDO_REG3#7IB@aB@yvdd_10regulator-state-memB@LDO_REG4#7Iw@aw@yvcc_wlregulator-state-memw@LDO_REG5#7Iw@a2Z yvccio_sdregulator-state-mem2ZLDO_REG6#7IB@aB@ yvdd10_lcdregulator-state-memB@LDO_REG7#7Iw@aw@yvcc_18regulator-state-memw@LDO_REG8#7Iw@aw@ yvcc18_lcdregulator-state-memw@SWITCH_REG1#7yvcc_sdregulator-state-memSWITCH_REG2#7yvcc_lanE2K2regulator-state-memi2c@ff660000rockchip,rk3288-i2cf =i2c2Nadefaulto= disabledpwm@ff680000rockchip,rk3288-pwmhadefaulto>2^pwm disabledpwm@ff680010rockchip,rk3288-pwmhadefaulto?2^pwm disabledpwm@ff680020rockchip,rk3288-pwmh adefaulto@2^pwm disabledpwm@ff680030rockchip,rk3288-pwmh0adefaultoA2^pwm disabledbus_intmem@ff700000 mmio-sramp Spsmp-sram@0rockchip,rk3066-smp-sramsram@ff720000#rockchip,rk3288-pmu-srammmio-sramrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfdsEKpower-controller!rockchip,rk3288-power-controllerzh EFKFpd_vio@9 2chgfdehilkjpd_hevc@11 2oppd_video@12 2pd_gpu@13 2reboot-modesyscon-reboot-modeRBRBRB %RBsyscon@ff740000rockchip,rk3288-sgrfsyscontclock-controller@ff760000rockchip,rk3288-cruvm,1Hzjk$>#gׄeрxhрxhEKsyscon@ff770000&rockchip,rk3288-grfsysconsimple-mfdwE,K,edp-phyrockchip,rk3288-dp-phy2h24mS disabledEQKQio-domains"rockchip,rk3288-io-voltage-domain disabledusbphyrockchip,rk3288-usb-phyokayadefaultoB ^8usb-phy@320S 2]phyclkE6K6usb-phy@334S42^phyclkE4K4usb-phy@348SH2_phyclkE5K5watchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt2p O disabledsound@ff88b0000,rockchip,rk3288-spdifrockchip,rk3066-spdifm hclkmclk2TCtx 6adefaultoDm, disabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s 5CCtxrxi2s_hclki2s_clk2RadefaultoE~ disabledcypto-controller@ff8a0000rockchip,rk3288-crypto@ 0 2}aclkhclksclkapb_pclk crypto-rstokayvop@ff930000rockchip,rk3288-vop 2aclk_vopdclk_vophclk_vopF def axiahbdclkGokayportE K endpoint@0HETKTendpoint@1IERKRendpoint@2JEOKOiommu@ff930300rockchip,iommu  ]vopb_mmuF okayEGKGvop@ff940000rockchip,rk3288-vop 2aclk_vopdclk_vophclk_vopF  axiahbdclkKokayportE K endpoint@0LEUKUendpoint@1MESKSendpoint@2NEPKPiommu@ff940300rockchip,iommu  ]vopl_mmuF okayEKKKmipi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi@ 2~d refpclkF m, disabledportsportendpoint@0OEJKJendpoint@1PENKNdp@ff970000rockchip,rk3288-dp@ b2icdppclkQdpodpm, disabledportsport@0endpoint@0REIKIendpoint@1SEMKMhdmi@ff980000rockchip,rk3288-dw-hdmim, g2hm iahbisfrF okayportsportendpoint@0TEHKHendpoint@1UELKLmali@ffa300004rockchip,rk3288-maliarm,mali-t760arm,mali-midgard$ ]jobmmugpu2VF  disabledgpu-opp-tableoperating-points-v2EVKVopp@100000000~opp@200000000 ~opp@300000000B@opp@400000000ׄopp@500000000eOopp@600000000#Finterrupt-controller@ffc01000 arm,gic-400#  @ `   EKefuse@ffb40000rockchip,rockchip-efuse 2q pclk_efusecpu_leakage@17pinctrlrockchip,rk3288-pinctrlm,Sgpio0@ff750000rockchip,gpio-banku Q2@4D#E8K8gpio1@ff780000rockchip,gpio-bankx R2A4D#gpio2@ff790000rockchip,gpio-banky S2B4D#gpio3@ff7a0000rockchip,gpio-bankz T2C4D#gpio4@ff7b0000rockchip,gpio-bank{ U2D4D#E3K3gpio5@ff7c0000rockchip,gpio-bank| V2E4D#gpio6@ff7d0000rockchip,gpio-bank} W2F4D#gpio7@ff7e0000rockchip,gpio-bank~ X2G4D#gpio8@ff7f0000rockchip,gpio-bank Y2H4D#hdmihdmi-ddc PWWpcfg-pull-up^EXKXpcfg-pull-downkEYKYpcfg-pull-nonezEWKWpcfg-pull-none-12maz EZKZsleepglobal-pwroffPWE:K:ddrio-pwroffPWddr0-retentionPXddr1-retentionPXedpedp-hpdP Yi2c0i2c0-xfer PWWE7K7i2c1i2c1-xfer PWWEKi2c2i2c2-xfer P W WE=K=i2c3i2c3-xfer PWWEKi2c4i2c4-xfer PWWEKi2c5i2c5-xfer PWWE K i2s0i2s0-bus`PWWWWWWEEKEsdmmcsdmmc-clkPWsdmmc-cmdPXsdmmc-cdPXsdmmc-bus1PXsdmmc-bus4@PXXXXsdio0sdio0-bus1PXsdio0-bus4@PXXXXsdio0-cmdPXsdio0-clkPWsdio0-cdPXsdio0-wpPXsdio0-pwrPXsdio0-bkpwrPXsdio0-intPXsdio1sdio1-bus1PXsdio1-bus4@PXXXXsdio1-cdPXsdio1-wpPXsdio1-bkpwrPXsdio1-intPXsdio1-cmdPXsdio1-clkPWsdio1-pwrP Xemmcemmc-clkPWE K emmc-cmdPXE K emmc-pwrP XEKemmc-bus1PXemmc-bus4@PXXXXemmc-bus8PXXXXXXXXEKspi0spi0-clkP XEKspi0-cs0P XEKspi0-txPXEKspi0-rxPXEKspi0-cs1PXspi1spi1-clkP XEKspi1-cs0P XEKspi1-rxPXEKspi1-txPXEKspi2spi2-cs1PXspi2-clkPXEKspi2-cs0PXEKspi2-rxPXEKspi2-txP XEKuart0uart0-xfer PXWE!K!uart0-ctsPXuart0-rtsPWuart1uart1-xfer PX WE"K"uart1-ctsP Xuart1-rtsP Wuart2uart2-xfer PXWE#K#uart3uart3-xfer PXWE$K$uart3-ctsP Xuart3-rtsP Wuart4uart4-xfer P X WE%K%uart4-ctsPXuart4-rtsPWtsadcotp-gpioP WE*K*otp-outP WE+K+pwm0pwm0-pinPWE>K>pwm1pwm1-pinPWE?K?pwm2pwm2-pinPWE@K@pwm3pwm3-pinPWEAKAgmacrgmii-pinsPWWWWZZZZWWW ZZWWE.K.rmii-pinsPWWWWWWWWWWphy-intP XE1K1phy-pmebPXE0K0phy-rstP[E/K/spdifspdif-txP WEDKDpcfg-output-highE[K[pcfg-output-lowpcfg-pull-none-drv-8mapcfg-pull-up-drv-8ma^pmicpmic-intPXE9K9usbphyhost-drvPWEBKBexternal-gmac-clock fixed-clocksY@ ext_gmacE-K-vsys-regulatorregulator-fixedyvcc_sysILK@aLK@#7E;K; #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2device_typereginterruptsinterrupt-affinityenable-methodrockchip,pmuresetsoperating-points#cooling-cellsclock-latencyclockscpu0-supplylinux,phandleranges#dma-cellsarm,pl330-broken-no-flushpclock-namesstatusclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredarm,no-tick-in-suspendportsclock-freq-min-maxfifo-depthbus-widthcap-mmc-highspeeddisable-wpnon-removablenum-slotspinctrl-namespinctrl-0#io-channel-cellsreset-namesdmasdma-namesreg-shiftreg-io-widthpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-tempinterrupt-namesrockchip,grfassigned-clocksassigned-clock-parentsclock_in_outphy-supplyphy-modesnps,reset-active-lowsnps,reset-delays-ussnps,reset-gpiotx_delayrx_delayphysphy-namesdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeg-use-dmarockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyvddio-supplyregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-nameregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvolt#pwm-cells#power-domain-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cellsvbus_drv-gpios#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channelspower-domainsiommusremote-endpoint#iommu-cellsoperating-points-v2opp-hzopp-microvoltinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsrockchip,pinsbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-low