@8=T(o=Altera SOCFPGA VT!altr,socfpga-vtaltr,socfpgachosen,console=ttyS0,57600aliases5/soc/ethernet@ff700000?/soc/ethernet@ff702000I/soc/serial0@ffc02000Q/soc/serial1@ffc03000Y/soc/timer0@ffc08000`/soc/timer1@ffc09000g/soc/timer2@ffd00000n/soc/timer3@ffd01000memoryumemory@cpusaltr,socfpga-smpcpu@0!arm,cortex-a9ucpucpu@1!arm,cortex-a9ucpuintc@fffed000!arm,cortex-a9-gicsoc !simple-bususocamba !simple-buspdma@ffe01000!arm,pl330arm,primecell`hijklmno " )apb_pclk))can@ffc00000 !bosch,d_can0" 5disabledcan@ffc01000 !bosch,d_can0" 5disabledclkmgr@ffd04000 !altr,clk-mgr@clocksosc1< !fixed-clockIosc2< !fixed-clockf2s_periph_ref_clk< !fixed-clock  f2s_sdram_ref_clk< !fixed-clock  main_pll<!altr,socfpga-pll-clock"@mpuclk<!altr,socfpga-perip-clk" Y H  mainclk<!altr,socfpga-perip-clk" Y Ldbg_base_clk<!altr,socfpga-perip-clk" Y Pmain_qspi_clk<!altr,socfpga-perip-clk"Tmain_nand_sdmmc_clk<!altr,socfpga-perip-clk"Xcfg_h2f_usr0_clk<!altr,socfpga-perip-clk"\periph_pll<!altr,socfpga-pll-clock "   emac0_clk<!altr,socfpga-perip-clk" emac1_clk<!altr,socfpga-perip-clk" per_qsi_clk<!altr,socfpga-perip-clk" per_nand_mmc_clk<!altr,socfpga-perip-clk" per_base_clk<!altr,socfpga-perip-clk" h2f_usr1_clk<!altr,socfpga-perip-clk" sdram_pll<!altr,socfpga-pll-clock "   ddr_dqs_clk<!altr,socfpga-perip-clk" ddr_2x_dqs_clk<!altr,socfpga-perip-clk" ddr_dq_clk<!altr,socfpga-perip-clk" h2f_usr2_clk<!altr,socfpga-perip-clk" mpu_periph_clk<!altr,socfpga-perip-clk" a((mpu_l2_ram_clk<!altr,socfpga-perip-clk" al4_main_clk<!altr,socfpga-gate-clk"o`l3_main_clk<!altr,socfpga-perip-clk"al3_mp_clk<!altr,socfpga-gate-clk" Ydo`l3_sp_clk<!altr,socfpga-gate-clk" Ydl4_mp_clk<!altr,socfpga-gate-clk" Ydo`""l4_sp_clk<!altr,socfpga-gate-clk" Ydo`##dbg_at_clk<!altr,socfpga-gate-clk" Yho`dbg_clk<!altr,socfpga-gate-clk" Yho`dbg_trace_clk<!altr,socfpga-gate-clk" Ylo`dbg_timer_clk<!altr,socfpga-gate-clk"o`cfg_clk<!altr,socfpga-gate-clk"o`h2f_user0_clk<!altr,socfpga-gate-clk"o` emac_0_clk<!altr,socfpga-gate-clk"oemac_1_clk<!altr,socfpga-gate-clk"ousb_mp_clk<!altr,socfpga-gate-clk"o Y**spi_m_clk<!altr,socfpga-gate-clk"o Y''can0_clk<!altr,socfpga-gate-clk"o Ycan1_clk<!altr,socfpga-gate-clk"o Y gpio_db_clk<!altr,socfpga-gate-clk"o Yh2f_user1_clk<!altr,socfpga-gate-clk"osdmmc_clk<!altr,socfpga-gate-clk " oxsdmmc_clk_divided<!altr,socfpga-gate-clk"oa%%nand_x_clk<!altr,socfpga-gate-clk " o nand_clk<!altr,socfpga-gate-clk " o aqspi_clk<!altr,socfpga-gate-clk " o ddr_dqs_clk_gate<!altr,socfpga-gate-clk"oddr_2x_dqs_clk_gate<!altr,socfpga-gate-clk"oddr_dq_clk_gate<!altr,socfpga-gate-clk"oh2f_user2_clk<!altr,socfpga-gate-clk"ofpgamgr@ff706000!altr,socfpga-fpga-mgrp` ethernet@ff7000000!altr,socfpga-stmmacsnps,dwmac-3.70asnps,dwmac  `p  smacirq" )stmmaceth!  stmmaceth 5okaygmiiethernet@ff7020000!altr,socfpga-stmmacsnps,dwmac-3.70asnps,dwmac  `p  xmacirq" )stmmaceth!! stmmaceth  5disabledgpio@ff708000!snps,dw-apb-gpiop"" 5disabledgpio-controller@0!snps,dw-apb-gpio-port 0< gpio@ff709000!snps,dw-apb-gpiop"" 5disabledgpio-controller@0!snps,dw-apb-gpio-port 0< gpio@ff70a000!snps,dw-apb-gpiop"" 5disabledgpio-controller@0!snps,dw-apb-gpio-port 0< i2c@ffc04000!snps,designware-i2c@"#  5disabledi2c@ffc05000!snps,designware-i2cP"#  5disabledi2c@ffc06000!snps,designware-i2c`"#  5disabledi2c@ffc07000!snps,designware-i2cp"#  5disabledeccmgr@ffd08140!altr,socfpga-ecc-managerl2-ecc@ffd08140!altr,socfpga-l2-eccЁ@$%ocram-ecc@ffd08144!altr,socfpga-ocram-eccЁDJ$l2-cache@fffef000!arm,pl310-cache &O] i ydwmmc0@ff704000!altr,socfpga-dw-mshcp@ ""%)biuciu 5disabledsram@ffff0000 !mmio-sram$$rstmgr@ffd05000 !altr,rst-mgrP!!snoop-control-unit@fffec000!arm,cortex-a9-scusdr@ffc25000!sysconP&&sdramedac!altr,sdram-edac& 'spi@fff00000!snps,dw-apb-ssi "' 5disabledspi@fff01000!snps,dw-apb-ssi "' 5disabledsysmgr@ffd08000!altr,sys-mgrsysconЀ@Ѐ  timer@fffec600!arm,cortex-a9-twd-timer  "(timer0@ffc08000!snps,dw-apb-timer "#)timerIjtimer1@ffc09000!snps,dw-apb-timer "#)timerIjtimer2@ffd00000!snps,dw-apb-timer ")timerIjtimer3@ffd01000!snps,dw-apb-timer ")timerIjserial0@ffc02000!snps,dw-apb-uart  /9"#F))KtxrxIpserial1@ffc03000!snps,dw-apb-uart0 /9"#F))KtxrxIpusbphy@0U!usb-nop-xceiv5okay++usb@ffb00000 !snps,dwc2 }"*)otg!"dwc2`+ eusb2-phy 5disabledusb@ffb40000 !snps,dwc2 "*)otg!#dwc2`+ eusb2-phy 5disabledwatchdog@ffd02000 !snps,dw-wdt  " 5disabledwatchdog@ffd03000 !snps,dw-wdt0 " 5disabled #address-cells#size-cellsmodelcompatiblebootargsethernet0ethernet1serial0serial1timer0timer1timer2timer3device_typeregenable-methodnext-level-cache#interrupt-cellsinterrupt-controllerlinux,phandleinterrupt-parentrangesinterrupts#dma-cells#dma-channels#dma-requestsclocksclock-namesstatus#clock-cellsclock-frequencydiv-regfixed-dividerclk-gateclk-phasealtr,sysmgr-sysconinterrupt-namesmac-addressresetsreset-namessnps,multicast-filter-binssnps,perfect-filter-entriestx-fifo-depthrx-fifo-depthphy-modegpio-controller#gpio-cellssnps,nr-gpiosiramcache-unifiedcache-levelarm,tag-latencyarm,data-latencyprefetch-dataprefetch-instrnum-slotsbroken-cdbus-widthcap-mmc-highspeedcap-sd-highspeed#reset-cellsaltr,modrst-offsetaltr,sdr-sysconnum-cscpu1-start-addrreg-shiftreg-io-widthdmasdma-names#phy-cellsphysphy-names