28.@(V.!,Rockchip RK3229 Evaluation board$2rockchip,rk3229-evbrockchip,rk3229chosenaliases=/serial@11010000E/serial@11020000M/serial@11030000memoryUmemorya`@cpuscpu@f00Ucpu2arm,cortex-a7ael sB@}@cpu@f01Ucpu2arm,cortex-a7aecpu@f02Ucpu2arm,cortex-a7aecpu@f03Ucpu2arm,cortex-a7aeamba 2simple-buspdma@110f00002arm,pl330arm,primecella@ apb_pclkarm-pmu2arm,cortex-a7-pmu0LMNOtimer2arm,armv7-timer0   n6oscillator 2fixed-clockn6xin24m2i2s1@100b0000(2rockchip,rk3228-i2srockchip,rk3066-i2sa @ i2s_clki2s_hclkQ?DtxrxNdefault\ fdisabledi2s0@100c0000(2rockchip,rk3228-i2srockchip,rk3066-i2sa @ i2s_clki2s_hclkP?  Dtxrx fdisabledi2s2@100e0000(2rockchip,rk3228-i2srockchip,rk3066-i2sa@ i2s_clki2s_hclkR?Dtxrx fdisabledsyscon@110000002sysconaserial@110100002snps,dw-apb-uarta 7n6MUbaudclkapb_pclkNdefault \ mw fdisabledserial@110200002snps,dw-apb-uarta 8n6NVbaudclkapb_pclkNdefault\ mw fdisabledserial@110300002snps,dw-apb-uarta 9n6OWbaudclkapb_pclkNdefault\ mwfokayi2c@110500002rockchip,rk3228-i2ca $i2cLNdefault\ fdisabledi2c@110600002rockchip,rk3228-i2ca %i2cMNdefault\ fdisabledi2c@110700002rockchip,rk3228-i2ca &i2cNNdefault\ fdisabledi2c@110800002rockchip,rk3228-i2ca 'i2cONdefault\ fdisabledpwm@110b00002rockchip,rk3288-pwma ^pwmNdefault\ fdisabledpwm@110b00102rockchip,rk3288-pwma ^pwmNdefault\ fdisabledpwm@110b00202rockchip,rk3288-pwma ^pwmNdefault\ fdisabledpwm@110b00302rockchip,rk3288-pwma 0^pwmNdefault\ fdisabledtimer@110c00002rockchip,rk3288-timera  + a timerpclkclock-controller@110e00002rockchip,rk3228-crua2#gthermal-zonescpu-thermaldtripscpu_alert0p\passivecpu_alert1$\passivecpu_crit_ \criticalcooling-mapsmap0 map1 tsadc@111500002rockchip,rk3228-tsadca :HXtsadcapb_pclkeW -tsadc-apbNinitdefaultsleep\9CMcs fdisableddwmmc@300200002rockchip,rk3288-dw-mshca0@ <4`z<4` Guybiuciuciu_drvciu_sampleNdefault \ fdisabledethernet@302000002rockchip,rk3228-gmaca0  macirq8~oMstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mace8 -stmmacethfokay}~  }input!rgmiiNdefault\"  # /'B@D0Minterrupt-controller@32010000 2arm,gic-400Vk a22 2@ 2`   pinctrl2rockchip,rk3228-pinctrlgpio0@111100002rockchip,gpio-banka 3@|Vkgpio1@111200002rockchip,gpio-banka 4A|Vkgpio2@111300002rockchip,gpio-banka 5B|Vk##gpio3@111400002rockchip,gpio-banka 6C|Vkpcfg-pull-uppcfg-pull-downpcfg-pull-none$$pcfg-pull-none-drv-12ma %%emmcemmc-clk$emmc-cmd$emmc-bus8$$$$$$$$gmacrgmii-pins$ $$%%%% % %$$$$ $$""rmii-pins$ $$%% %$$$$phy-pins $$i2c0i2c0-xfer $$i2c1i2c1-xfer $$i2c2i2c2-xfer $$i2c3i2c3-xfer $$i2s1i2s1-bus$ $ $ $ $$$$$pwm0pwm0-pin$pwm1pwm1-pin$pwm2pwm2-pin $pwm3pwm3-pin $tsadcotp-gpio$otp-out$uart0uart0-xfer $$  uart0-cts$  uart0-rts$  uart1uart1-xfer  $ $  uart1-cts$uart1-rts $uart2uart2-xfer $$  uart2-cts$uart2-rts$ext_gmac 2fixed-clocksY@ ext_gmac2  vcc-phy-regulator2regulator-fixedvcc_phyw@w@0D!! #address-cells#size-cellsinterrupt-parentmodelcompatibleserial0serial1serial2device_typeregresetsoperating-points#cooling-cellsclock-latencyclockslinux,phandlerangesinterrupts#dma-cellsclock-namesinterrupt-affinityarm,cpu-registers-not-fw-configuredclock-frequencyclock-output-names#clock-cellsdmasdma-namespinctrl-namespinctrl-0statusreg-shiftreg-io-width#pwm-cellsrockchip,grf#reset-cellsassigned-clocksassigned-clock-ratespolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicereset-namespinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-tempclock-freq-min-maxbus-widthdefault-sample-phasenum-slotsfifo-depthinterrupt-namesassigned-clock-parentsclock_in_outphy-supplyphy-modesnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ustx_delayrx_delayinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthrockchip,pinsenable-active-highregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-on