Ð þíQ8Kx(–K@,radxa,rockrockchip,rk3188 7Radxa Rockchosenaliases=/ethernet@10204000G/i2c@2002d000L/i2c@2002f000Q/i2c@20056000V/i2c@2005a000[/i2c@2005e000`/dwmmc@1021c000f/dwmmc@10214000l/dwmmc@10218000r/serial@10124000z/serial@10126000‚/serial@20064000Š/serial@20068000’/spi@20070000—/spi@20074000memoryœmemory¨`€amba ,simple-bus¬dma-controller@20018000,arm,pl330arm,primecell¨ €@³¾ÉäÀ ëapb_pclk÷/ý/dma-controller@2001c000,arm,pl330arm,primecell¨ À@³¾ÉäÀ ëapb_pclk disableddma-controller@20078000,arm,pl330arm,primecell¨ €@³¾ÉäÁ ëapb_pclk÷#ý#oscillator ,fixed-clock n6)xin24ml2-cache-controller@10138000,arm,pl310-cache¨€<J÷,ý,scu@1013c000,arm,cortex-a9-scu¨Àglobal-timer@1013c200,arm,cortex-a9-global-timer¨  ³ älocal-timer@1013c600,arm,cortex-a9-twd-timer¨Æ  ³ äinterrupt-controller@1013d000,arm,cortex-a9-gicVk¨ÐÁ÷ýserial@10124000,snps,dw-apb-uart¨@ ³"|†ëbaudclkapb_pclkä@Lokay“default¡serial@10126000,snps,dw-apb-uart¨` ³#|†ëbaudclkapb_pclkäAMokay“default¡usb@10180000,rockchip,rk3066-usbsnps,dwc2¨ ³äÃëotg«otg³ÅÔ€€@@ ãí òusb2-phyokayusb@101c0000 ,snps,dwc2¨ ³äÉëotg«hostí òusb2-phyokayethernet@10204000,rockchip,rk3188-emac¨ @< ³üäÄD ëhclkmacref drmiiokay“default ¡   ethernet-phy@0¨ ³÷ ý dwmmc@10214000,rockchip,rk2928-dw-mshc¨!@ ³äÀHëbiuciu+okay6“default¡@LVhydwmmc@10218000,rockchip,rk2928-dw-mshc¨!€ ³äÁIëbiuciu+ disableddwmmc@1021c000,rockchip,rk2928-dw-mshc¨!À ³äÂJëbiuciu+ disabledpmu@20004000&,rockchip,rk3066-pmusysconsimple-mfd¨ @÷1ý1reboot-mode,syscon-reboot-mode„@‹RB×RBÃ¥RBà µRBÃgrf@20008000,syscon¨ €÷ýi2c@2002d000,rockchip,rk3188-i2c¨ Ð ³(üëi2cäP disabled“default¡i2c@2002f000,rockchip,rk3188-i2c¨ ð ³)üäQëi2cokay“default¡ €rtc@51,haoyu,hym8563¨Q³ “default¡)xin32kact8846@5a,active-semi,act8846¨ZokayÁ“default¡ÙäïúregulatorsREG1)VCC_DDR8O€PO€hREG2)VDD_LOG8B@PB@hREG3)VDD_ARM8 YøP™ph÷-ý-REG4)VCC_IO82Z P2Z h÷ýREG5)VDD_108B@PB@hREG6 )VDD_HDMI8&% P&% hREG7)VCC_188w@Pw@hREG8)VCCA_3382Z P2Z hREG9 )VCC_RMII82Z P2Z ÷ ý REG10 )VCCIO_WL82Z P2Z hREG11 )VCC18_IO8w@Pw@hREG12)VCC_288*¹€P*¹€hpwm@20030000,rockchip,rk2928-pwm¨ |äF disabled“default¡pwm@20030010,rockchip,rk2928-pwm¨ |äFokay“default¡watchdog@2004c000 ,rockchip,rk3188-wdtsnps,dw-wdt¨ ÀäK ³3okaypwm@20050020,rockchip,rk2928-pwm¨  |äGokay“default¡pwm@20050030,rockchip,rk2928-pwm¨ 0|äGokay“default¡i2c@20056000,rockchip,rk3188-i2c¨ ` ³*üäRëi2c disabled“default¡i2c@2005a000,rockchip,rk3188-i2c¨   ³+üäSëi2c disabled“default¡i2c@2005e000,rockchip,rk3188-i2c¨ à ³4üäTëi2c disabled“default¡ serial@20064000,snps,dw-apb-uart¨ @ ³$|†ëbaudclkapb_pclkäBNokay“default¡!serial@20068000,snps,dw-apb-uart¨ € ³%|†ëbaudclkapb_pclkäCOokay“default¡"saradc@2006c000,rockchip,saradc¨ À ³‡äGJësaradcapb_pclk™W  saradc-apb disabledspi@20070000(,rockchip,rk3188-spirockchip,rk3066-spiäEHëspiclkapb_pclk ³&¨ ¬# # ±txrx disabled“default¡$%&'spi@20074000(,rockchip,rk3188-spirockchip,rk3066-spiäFIëspiclkapb_pclk ³'¨ @¬# # ±txrx disabled“default¡()*+cpus»rockchip,rk3066-smpcpu@0œcpu,arm,cortex-a9É,¨@Ú‰@™p›@ÐO€Œ0a€g8 s€à˜ 'À~ð°ÀHÂÀ Yøëœ@äù-cpu@1œcpu,arm,cortex-a9É,¨cpu@2œcpu,arm,cortex-a9É,¨cpu@3œcpu,arm,cortex-a9É,¨sram@10080000 ,mmio-sram¨€ ¬€smp-sram@0,rockchip,rk3066-smp-sram¨Pi2s@1011a000(,rockchip,rk3188-i2srockchip,rk3066-i2s¨   ³ “default¡.¬//±txrxëi2s_hclki2s_clkäÆK  disabledsound@1011e000,,rockchip,rk3188-spdifrockchip,rk3066-spdif¨à : ëhclkmclkäÅN¬/±tx ³ “default¡0okay÷5ý5clock-controller@20000000,rockchip,rk3188-cru¨ üK÷ýefuse@20010000,rockchip,rockchip-efuse¨ @ä[ ëpclk_efusecpu_leakage@17¨phy0,rockchip,rk3188-usb-phyrockchip,rk3288-usb-phyüokayusb-phy@10cX¨ äQëphyclk÷ýusb-phy@11cX¨äRëphyclk÷ýpinctrl,rockchip,rk3188-pinctrlüc1¬gpio0@2000a000,rockchip,rk3188-gpio-bank0¨   ³6äUp€Vk÷ýgpio1@2003c000,rockchip,gpio-bank¨ À ³7äVp€Vkgpio2@2003e000,rockchip,gpio-bank¨ à ³8äWp€Vk÷8ý8gpio3@20080000,rockchip,gpio-bank¨  ³9äXp€Vk÷ ý pcfg_pull_upŒ÷3ý3pcfg_pull_down™pcfg_pull_none¨÷2ý2emmcemmc-clkµ2emmc-cmdµ3emmc-rstµ2emacemac-xfer€µ22222222÷ýemac-mdio µ22÷ ý i2c0i2c0-xfer µ22÷ýi2c1i2c1-xfer µ22÷ýi2c2i2c2-xfer µ22÷ýi2c3i2c3-xfer µ22÷ýi2c4i2c4-xfer µ22÷ ý pwm0pwm0-outµ2÷ýpwm1pwm1-outµ2÷ýpwm2pwm2-outµ2÷ýpwm3pwm3-outµ2÷ýspi0spi0-clkµ3÷$ý$spi0-cs0µ3÷'ý'spi0-txµ3÷%ý%spi0-rxµ3÷&ý&spi0-cs1µ3spi1spi1-clkµ3÷(ý(spi1-cs0µ3÷+ý+spi1-rxµ3÷*ý*spi1-txµ3÷)ý)spi1-cs1µ3uart0uart0-xfer µ32÷ýuart0-ctsµ2uart0-rtsµ2uart1uart1-xfer µ32÷ýuart1-ctsµ2uart1-rtsµ2uart2uart2-xfer µ3 2÷!ý!uart3uart3-xfer µ 3 2÷"ý"uart3-ctsµ 2uart3-rtsµ 2sd0sd0-clkµ2÷ýsd0-cmdµ2÷ýsd0-cdµ2÷ýsd0-wpµ 2sd0-pwrµ2sd0-bus-width1µ2sd0-bus-width4@µ2222÷ýsd1sd1-clkµ2sd1-cmdµ2sd1-cdµ2sd1-wpµ2sd1-bus-width1µ2sd1-bus-width4@µ2222i2s0i2s0-bus`µ222222÷.ý.spdifspdif-txµ2÷0ý0pcfg-output-lowÃ÷4ý4act8846act8846-dvs0-ctlµ4÷ýhym8563rtc-intµ3÷ýlan8720aphy-intµ3÷ ý ir-receiverir-recv-pinµ 2÷7ý7usbhost-vbus-drvµ2÷:ý:otg-vbus-drvµ2÷9ý9gpio-keys ,gpio-keysÎpower ÙßtêGPIO Key Powerðdgpio-leds ,gpio-ledsgreenêrock:green:user1 Ù !offblueêrock:blue:user2 Ù!offsleepêrock:red:power Ù!offsound,simple-audio-card/SPDIFsimple-audio-card,dai-link@1cpuF5codecF6spdif-out,linux,spdif-dit:÷6ý6gpio-ir-receiver,gpio-ir-receiver Ù “default¡7usb-otg-regulator,regulator-fixedP c8“default¡9 )otg-vbus8LK@PLK@hhsdmmc-regulator,regulator-fixed )sdmmc-supply82Z P2Z  c z† ‹÷ýusb-host-regulator,regulator-fixedP c“default¡: )host-pwr8LK@PLK@hhvsys-regulator,regulator-fixed)vsys8LK@PLK@h÷ý #address-cells#size-cellsinterrupt-parentcompatiblemodelethernet0i2c0i2c1i2c2i2c3i2c4mshc0mshc1mshc2serial0serial1serial2serial3spi0spi1device_typeregrangesinterrupts#dma-cellsarm,pl330-broken-no-flushpclocksclock-nameslinux,phandlestatusclock-frequency#clock-cellsclock-output-namescache-unifiedcache-levelinterrupt-controller#interrupt-cellsreg-shiftreg-io-widthpinctrl-namespinctrl-0dr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeg-use-dmaphysphy-namesrockchip,grfmax-speedphy-modephyphy-supplyfifo-depthnum-slotsvmmc-supplybus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpoffsetmode-normalmode-recoverymode-bootloadermode-loadersystem-power-controllervp1-supplyvp2-supplyvp3-supplyvp4-supplyinl1-supplyinl2-supplyinl3-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-on#pwm-cells#io-channel-cellsresetsreset-namesdmasdma-namesenable-methodnext-level-cacheoperating-pointsclock-latencycpu0-supplyrockchip,playback-channelsrockchip,capture-channels#sound-dai-cells#reset-cells#phy-cellsrockchip,pmugpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disablerockchip,pinsoutput-lowautorepeatgpioslinux,codelabellinux,input-typewakeup-sourcedebounce-intervaldefault-statesimple-audio-card,namesound-daienable-active-highgpioregulator-boot-onstartup-delay-usvin-supply