^8Y@(^Y(,chipspark,rayeager-px2rockchip,rk3066a 7Rayeager PX2chosenaliases=/ethernet@10204000G/i2c@2002d000L/i2c@2002f000Q/i2c@20056000V/i2c@2005a000[/i2c@2005e000`/dwmmc@1021c000f/dwmmc@10214000l/dwmmc@10218000r/serial@10124000z/serial@10126000/serial@20064000/serial@20068000/spi@20070000/spi@20074000memorymemory`@amba ,simple-busdma-controller@20018000,arm,pl330arm,primecell @ apb_pclk@@dma-controller@2001c000,arm,pl330arm,primecell @ apb_pclk disableddma-controller@20078000,arm,pl330arm,primecell @ apb_pclk44oscillator ,fixed-clock n6)xin24ml2-cache-controller@10138000,arm,pl310-cache<J==scu@1013c000,arm,cortex-a9-scuglobal-timer@1013c200,arm,cortex-a9-global-timer   local-timer@1013c600,arm,cortex-a9-twd-timer   interrupt-controller@1013d000,arm,cortex-a9-gicVkserial@10124000,snps,dw-apb-uart@ "|baudclkapb_pclk@Lokaydefault serial@10126000,snps,dw-apb-uart` #|baudclkapb_pclkAM disableddefaultusb@10180000,rockchip,rk3066-usbsnps,dwc2 otgotg@@  usb2-phyokayusb@101c0000 ,snps,dwc2 otghost usb2-phyokaydefault ethernet@10204000,rockchip,rk3066-emac @<  D hclkmacref drmiiokaydefault   ethernet-phy@0dwmmc@10214000,rockchip,rk2928-dw-mshc!@ Hbiuciu+okaydefault6@KUasdwmmc@10218000,rockchip,rk2928-dw-mshc! Ibiuciu+okaydefault 6@KUdwmmc@1021c000,rockchip,rk2928-dw-mshc! Jbiuciu+okay6a@Kdefault Upmu@20004000&,rockchip,rk3066-pmusysconsimple-mfd @reboot-mode,syscon-reboot-mode@RBRBRB RBgrf@20008000,syscon   i2c@2002d000,rockchip,rk3066-i2c  ( i2cPokaydefault ak8963@0d,asahi-kasei,ak8975 default mma8452@1d ,fsl,mma8452default!i2c@2002f000,rockchip,rk3066-i2c  ) Qi2cokaydefault" tps@2d-#default$%&&&& ''$&0& ,ti,tps65910regulatorsregulator@0=vcc_rtcL`vrtcregulator@1=vcc_iou2Z2ZL`vio''regulator@2=vdd_armu '`L`vdd1>>regulator@3=vcc_ddru '`L`vdd2regulator@5=vcc18uw@w@L`vdig1regulator@6=vdd_11uL`vdig2regulator@7=vcc_25u&%&%L`vpll33regulator@8 =vccio_wluw@w@`vdacregulator@9 =vcc25_hdmiu&%&% `vaux1regulator@10=vcca_33u2Z2Z `vaux2regulator@11 =vcc_rmiiu2Z2Z `vaux33regulator@12 =vcc28_cifu** `vmmcregulator@4`vdd3regulator@13 `vbbpwm@20030000,rockchip,rk2928-pwm F disableddefault(pwm@20030010,rockchip,rk2928-pwm Fokaydefault)watchdog@2004c000 ,rockchip,rk3066-wdtsnps,dw-wdt K 3okaypwm@20050020,rockchip,rk2928-pwm  Gokaydefault*pwm@20050030,rockchip,rk2928-pwm 0Gokaydefault+HHi2c@20056000,rockchip,rk3066-i2c ` * Ri2cokaydefault,i2c@2005a000,rockchip,rk3066-i2c  + Si2cokaydefault-i2c@2005e000,rockchip,rk3066-i2c  4 Ti2cokaydefault.serial@20064000,snps,dw-apb-uart @ $|baudclkapb_pclkBNokaydefault/serial@20068000,snps,dw-apb-uart  %|baudclkapb_pclkCOokaydefault 012saradc@2006c000,rockchip,saradc  GJsaradcapb_pclkW saradc-apbokay3spi@20070000,rockchip,rk3066-spiEHspiclkapb_pclk & 4 4 txrxokaydefault5678spi@20074000,rockchip,rk3066-spiFIspiclkapb_pclk ' @4 4 txrx disableddefault9:;<cpusrockchip,rk3066-smpcpu@0cpu,arm,cortex-a9=8!@ Oa* s* 'g82@@>cpu@1cpu,arm,cortex-a9=sram@10080000 ,mmio-sram smp-sram@0,rockchip,rk3066-smp-sramPi2s@10118000,rockchip,rk3066-i2s  default?@@txrxi2s_hclki2s_clkKLg disabledi2s@1011a000,rockchip,rk3066-i2s  defaultA@@txrxi2s_hclki2s_clkLLg disabledi2s@1011c000,rockchip,rk3066-i2s  defaultB@ @ txrxi2s_hclki2s_clkMLg disabledclock-controller@20000000,rockchip,rk3066a-cru  timer@2000e000,snps,dw-apb-timer-osc  .VD timerpclkefuse@20010000,rockchip,rockchip-efuse @[ pclk_efusecpu_leakage@17timer@20038000,snps,dw-apb-timer-osc  ,TB timerpclktimer@2003a000,snps,dw-apb-timer-osc  -UC timerpclktsadc@20060000,rockchip,rk3066-tsadc ]]saradcapb_pclk W saradc-apb disabledphy1,rockchip,rk3066a-usb-phyrockchip,rk3288-usb-phy okayusb-phy@17c|Qphyclkusb-phy@188Rphyclkpinctrl,rockchip,rk3066a-pinctrl gpio0@20034000,rockchip,gpio-bank @ 6UVkMMgpio1@2003c000,rockchip,gpio-bank  7VVkgpio2@2003e000,rockchip,gpio-bank  8WVkgpio3@20080000,rockchip,gpio-bank  9XVkKKgpio4@20084000,rockchip,gpio-bank @ :YVkgpio6@2000a000,rockchip,gpio-bank  <ZVk##pcfg_pull_defaultEEpcfg_pull_noneCCemacemac-xferCCCCCCCC  emac-mdio CC  rmii-rstDemmcemmc-clkEemmc-cmd Eemmc-rst Ei2c0i2c0-xfer CCi2c1i2c1-xfer CC""i2c2i2c2-xfer CC,,i2c3i2c3-xfer CC--i2c4i2c4-xfer CC..pwm0pwm0-outC((pwm1pwm1-outC))pwm2pwm2-outC**pwm3pwm3-outC++spi0spi0-clkE55spi0-cs0E88spi0-txE66spi0-rxE77spi0-cs1Espi1spi1-clkE99spi1-cs0E<<spi1-rxE;;spi1-txE::spi1-cs1Euart0uart0-xfer EEuart0-ctsEuart0-rtsEuart1uart1-xfer EEuart1-ctsEuart1-rtsEuart2uart2-xfer E E//uart3uart3-xfer EE00uart3-ctsE11uart3-rtsE22sd0sd0-clkEsd0-cmd Esd0-cdEsd0-wpEsd0-bus-width1 Esd0-bus-width4@ E E E Esd1sd1-clkEsd1-cmdEsd1-cdEsd1-wpEsd1-bus-width1Esd1-bus-width4@EEEEi2s0i2s0-busEE E E E E EEE??i2s1i2s1-bus`EEEEEEAAi2s2i2s2-bus`EEEEEEBBpcfg-output-highDDak8963comp-intE  irir-intEFFkeyspwr-keyEGGmma8452gsensor-intE!!mmcsdmmc-pwrELLusb_hosthost-drvENNhub-rstD  sata-pwrEIIsata-reset D  usb_otgotg-drvEOOtpspmic-intE$$pwr-holdD%%ir-receiver,gpio-ir-receiver #defaultFgpio-keys ,gpio-keyspower # GPIO Power tdefaultGvdd-log,pwm-regulator H=vdd_loguOOLB@dO*okayvsys-regulator,regulator-fixed=vsysuLK@LK@L&&5v-stdby-regulator,regulator-fixed =5v_stdbyuLK@LK@LJJemmc-regulator,regulator-fixed =emmc_vccqu--*&sata-regulator,regulator-fixed5 HdefaultI=usb_5vuLK@LK@L*Jsdmmc-regulator,regulator-fixed HKdefaultL=vcc_sdu2Z2ZM*'usb-host-regulator,regulator-fixed5 HMdefaultN =host-pwruLK@LK@L*Jusb-otg-regulator,regulator-fixed5 HMdefaultO=vcc_otguLK@LK@L*J #address-cells#size-cellsinterrupt-parentcompatiblemodelethernet0i2c0i2c1i2c2i2c3i2c4mshc0mshc1mshc2serial0serial1serial2serial3spi0spi1device_typeregrangesinterrupts#dma-cellsarm,pl330-broken-no-flushpclocksclock-nameslinux,phandlestatusclock-frequency#clock-cellsclock-output-namescache-unifiedcache-levelinterrupt-controller#interrupt-cellsreg-shiftreg-io-widthpinctrl-namespinctrl-0dr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeg-use-dmaphysphy-namesrockchip,grfmax-speedphy-modephyphy-supplyfifo-depthbus-widthdisable-wpnum-slotsvmmc-supplycap-mmc-highspeedcap-sd-highspeednon-removablevqmmc-supplyoffsetmode-normalmode-recoverymode-bootloadermode-loadervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvccio-supplyregulator-nameregulator-always-onregulator-compatibleregulator-min-microvoltregulator-max-microvoltregulator-boot-on#pwm-cells#io-channel-cellsresetsreset-namesvref-supplydmasdma-namesenable-methodnext-level-cacheoperating-pointsclock-latencycpu0-supplyrockchip,playback-channelsrockchip,capture-channels#reset-cells#phy-cellsgpio-controller#gpio-cellsbias-pull-pin-defaultbias-disablerockchip,pinsoutput-highgpioswakeup-sourcelabellinux,codepwmsvoltage-tablevin-supplyenable-active-highgpiostartup-delay-us