Ð þíO 8J¤(üJl',mundoreader,bq-curie2rockchip,rk3066a 7bq Curie 2chosenaliases=/ethernet@10204000G/i2c@2002d000L/i2c@2002f000Q/i2c@20056000V/i2c@2005a000[/i2c@2005e000`/dwmmc@1021c000f/dwmmc@10214000l/dwmmc@10218000r/serial@10124000z/serial@10126000‚/serial@20064000Š/serial@20068000’/spi@20070000—/spi@20074000memoryœmemory¨`@amba ,simple-bus¬dma-controller@20018000,arm,pl330arm,primecell¨ €@³¾ÉäÀ ëapb_pclk÷)ý)dma-controller@2001c000,arm,pl330arm,primecell¨ À@³¾ÉäÀ ëapb_pclk disableddma-controller@20078000,arm,pl330arm,primecell¨ €@³¾ÉäÁ ëapb_pclk÷ýoscillator ,fixed-clock n6)xin24ml2-cache-controller@10138000,arm,pl310-cache¨€<J÷&ý&scu@1013c000,arm,cortex-a9-scu¨Àglobal-timer@1013c200,arm,cortex-a9-global-timer¨  ³ älocal-timer@1013c600,arm,cortex-a9-twd-timer¨Æ  ³ äinterrupt-controller@1013d000,arm,cortex-a9-gicVk¨ÐÁ÷ýserial@10124000,snps,dw-apb-uart¨@ ³"|†ëbaudclkapb_pclkä@Lokay“default¡serial@10126000,snps,dw-apb-uart¨` ³#|†ëbaudclkapb_pclkäAMokay“default¡usb@10180000,rockchip,rk3066-usbsnps,dwc2¨ ³äÃëotg«otg³ÅÔ€€@@ ãí òusb2-phy disabledusb@101c0000 ,snps,dwc2¨ ³äÉëotg«hostí òusb2-phy disabledethernet@10204000,rockchip,rk3066-emac¨ @< ³üäÄD ëhclkmacref drmii disableddwmmc@10214000,rockchip,rk2928-dw-mshc¨!@ ³äÀHëbiuciuokay“default¡ '1 =GYjdwmmc@10218000,rockchip,rk2928-dw-mshc¨!€ ³äÁIëbiuciuokay“default ¡ 'u=jdwmmc@1021c000,rockchip,rk2928-dw-mshc¨!À ³äÂJëbiuciu disabledpmu@20004000&,rockchip,rk3066-pmusysconsimple-mfd¨ @reboot-mode,syscon-reboot-modeƒ@ŠRBÖRBäRBà ´RBÃgrf@20008000,syscon¨ €÷ýi2c@2002d000,rockchip,rk3066-i2c¨ Ð ³(üëi2cäP disabled“default¡i2c@2002f000,rockchip,rk3066-i2c¨ ð ³)üäQëi2cokay“default¡ €tps@2d¨-³ÀÌ ,ti,tps65910regulatorsregulator@0Øvcc_rtcç¨ûvrtcregulator@1Øvcc_ioç¨ûvio÷ýregulator@2Øvdd_arm 'À(ã`@ç¨ûvdd1÷'ý'regulator@3Øvcc_ddr 'À(ã`@ç¨ûvdd2regulator@5 Øvcc18_cifç¨ûvdig1regulator@6Øvdd_11ç¨ûvdig2regulator@7Øvcc_25ç¨ûvpllregulator@8Øvcc_18ç¨ûvdacregulator@9 Øvcc25_hdmiç¨ ûvaux1regulator@10Øvcca_33ç¨ ûvaux2regulator@11Øvcc_tpç¨ ûvaux33regulator@12 Øvcc28_cifç¨ ûvmmcregulator@4¨ûvdd3regulator@13¨ ûvbbpwm@20030000,rockchip,rk2928-pwm¨ RäF disabled“default¡pwm@20030010,rockchip,rk2928-pwm¨ RäF disabled“default¡watchdog@2004c000 ,rockchip,rk3066-wdtsnps,dw-wdt¨ ÀäK ³3okaypwm@20050020,rockchip,rk2928-pwm¨  RäG disabled“default¡pwm@20050030,rockchip,rk2928-pwm¨ 0RäGokay“default¡÷.ý.i2c@20056000,rockchip,rk3066-i2c¨ ` ³*üäRëi2c disabled“default¡i2c@2005a000,rockchip,rk3066-i2c¨   ³+üäSëi2c disabled“default¡i2c@2005e000,rockchip,rk3066-i2c¨ à ³4üäTëi2c disabled“default¡serial@20064000,snps,dw-apb-uart¨ @ ³$|†ëbaudclkapb_pclkäBNokay“default¡serial@20068000,snps,dw-apb-uart¨ € ³%|†ëbaudclkapb_pclkäCOokay“default¡saradc@2006c000,rockchip,saradc¨ À ³]äGJësaradcapb_pclkoW vsaradc-apb disabledspi@20070000,rockchip,rk3066-spiäEHëspiclkapb_pclk ³&¨ ‚  ‡txrx disabled“default¡ !spi@20074000,rockchip,rk3066-spiäFIëspiclkapb_pclk ³'¨ @‚  ‡txrx disabled“default¡"#$%cpus‘rockchip,rk3066-smpcpu@0œcpu,arm,cortex-a9Ÿ&¨8°›@Ö O€íØa€*ˆ s€*ˆ 'ÀÈà°ÀÈàÂÀg8Áœ@äÏ'cpu@1œcpu,arm,cortex-a9Ÿ&¨sram@10080000 ,mmio-sram¨ ¬smp-sram@0,rockchip,rk3066-smp-sram¨Pi2s@10118000,rockchip,rk3066-i2s¨€  ³“default¡(‚))‡txrxëi2s_hclki2s_clkäÆKÛö disabledi2s@1011a000,rockchip,rk3066-i2s¨   ³ “default¡*‚))‡txrxëi2s_hclki2s_clkäÇLÛö disabledi2s@1011c000,rockchip,rk3066-i2s¨À  ³“default¡+‚) ) ‡txrxëi2s_hclki2s_clkäÈMÛö disabledclock-controller@20000000,rockchip,rk3066a-cru¨ ü÷ýtimer@2000e000,snps,dw-apb-timer-osc¨ à ³.äVD ëtimerpclkefuse@20010000,rockchip,rockchip-efuse¨ @ä[ ëpclk_efusecpu_leakage@17¨timer@20038000,snps,dw-apb-timer-osc¨ € ³,äTB ëtimerpclktimer@2003a000,snps,dw-apb-timer-osc¨   ³-äUC ëtimerpclktsadc@20060000,rockchip,rk3066-tsadc¨ ä]]ësaradcapb_pclk ³]oW vsaradc-apb disabledphy1,rockchip,rk3066a-usb-phyrockchip,rk3288-usb-phyü disabledusb-phy@17c¨|äQëphyclk÷ýusb-phy@188¨ˆäRëphyclk÷ýpinctrl,rockchip,rk3066a-pinctrlü¬gpio0@20034000,rockchip,gpio-bank¨ @ ³6äU(8Vkgpio1@2003c000,rockchip,gpio-bank¨ À ³7äV(8Vkgpio2@2003e000,rockchip,gpio-bank¨ à ³8äW(8Vkgpio3@20080000,rockchip,gpio-bank¨  ³9äX(8Vk÷/ý/gpio4@20084000,rockchip,gpio-bank¨ @ ³:äY(8Vk÷0ý0gpio6@2000a000,rockchip,gpio-bank¨   ³<äZ(8Vk÷ýpcfg_pull_defaultD÷-ý-pcfg_pull_noneZ÷,ý,emacemac-xfer€g,,,,,,,,emac-mdio g,,emmcemmc-clkg-emmc-cmdg -emmc-rstg -i2c0i2c0-xfer g,,÷ýi2c1i2c1-xfer g,,÷ýi2c2i2c2-xfer g,,÷ýi2c3i2c3-xfer g,,÷ýi2c4i2c4-xfer g,,÷ýpwm0pwm0-outg,÷ýpwm1pwm1-outg,÷ýpwm2pwm2-outg,÷ýpwm3pwm3-outg,÷ýspi0spi0-clkg-÷ýspi0-cs0g-÷!ý!spi0-txg-÷ýspi0-rxg-÷ ý spi0-cs1g-spi1spi1-clkg-÷"ý"spi1-cs0g-÷%ý%spi1-rxg-÷$ý$spi1-txg-÷#ý#spi1-cs1g-uart0uart0-xfer g--÷ýuart0-ctsg-uart0-rtsg-uart1uart1-xfer g--÷ýuart1-ctsg-uart1-rtsg-uart2uart2-xfer g- -÷ýuart3uart3-xfer g--÷ýuart3-ctsg-uart3-rtsg-sd0sd0-clkg-÷ýsd0-cmdg -÷ ý sd0-cdg-÷ ý sd0-wpg-sd0-bus-width1g -sd0-bus-width4@g - - - -÷ ý sd1sd1-clkg-÷ ý sd1-cmdg-÷ýsd1-cdg-sd1-wpg-sd1-bus-width1g-sd1-bus-width4@g----÷ýi2s0i2s0-busg-- - - - - ---÷(ý(i2s1i2s1-bus`g------÷*ý*i2s2i2s2-bus`g------÷+ý+vdd-log,pwm-regulator u.èØvdd_logO€(O€çzB@dO€*okayfixed-regulator,regulator-fixed Øsdmmc-supply-ÆÀ(-ÆÀ ˆ/† ž÷ ý gpio-keys ,gpio-keys©power ´ºtÅGPIO Key PowerËÜêdvolume-down ´0ºrÅGPIO Key Vol-Ëêd #address-cells#size-cellsinterrupt-parentcompatiblemodelethernet0i2c0i2c1i2c2i2c3i2c4mshc0mshc1mshc2serial0serial1serial2serial3spi0spi1device_typeregrangesinterrupts#dma-cellsarm,pl330-broken-no-flushpclocksclock-nameslinux,phandlestatusclock-frequency#clock-cellsclock-output-namescache-unifiedcache-levelinterrupt-controller#interrupt-cellsreg-shiftreg-io-widthpinctrl-namespinctrl-0dr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeg-use-dmaphysphy-namesrockchip,grfmax-speedphy-modefifo-depthnum-slotsvmmc-supplybus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpnon-removableoffsetmode-normalmode-recoverymode-bootloadermode-loadervcc5-supplyvcc6-supplyregulator-nameregulator-always-onregulator-compatibleregulator-min-microvoltregulator-max-microvoltregulator-boot-on#pwm-cells#io-channel-cellsresetsreset-namesdmasdma-namesenable-methodnext-level-cacheoperating-pointsclock-latencycpu0-supplyrockchip,playback-channelsrockchip,capture-channels#reset-cells#phy-cellsgpio-controller#gpio-cellsbias-pull-pin-defaultbias-disablerockchip,pinspwmsvoltage-tablegpiostartup-delay-usvin-supplyautorepeatgpioslinux,codelabellinux,input-typewakeup-sourcedebounce-interval