8 ( "ti,omap4-sdpti,omap4430ti,omap4 +7TI OMAP4 SDP boardchosenaliases=/ocp/i2c@48070000B/ocp/i2c@48072000G/ocp/i2c@48060000L/ocp/i2c@48350000Q/ocp/serial@4806a000Y/ocp/serial@4806c000a/ocp/serial@48020000i/ocp/serial@4806e000+q/ocp/dss@58000000/encoder@58004000/display+z/ocp/dss@58000000/encoder@58005000/display /connectorcpus+cpu@0arm,cortex-a9cpucpu  'O 5acpu@1arm,cortex-a9cpuinterrupt-controller@48241000arm,cortex-a9-gic 5H$H$ l2-cache-controller@48242000arm,pl310-cacheH$ FTlocal-timer@48240600arm,cortex-a9-twd-timerH$  `  interrupt-controller@48281000ti,omap4-wugen-mpu 5H( socti,omap-inframpu ti,omap4-mpukmpuudsp ti,omap3-c64kdspiva ti,ivahdkivaocpti,omap4-l3-nocsimple-bus+zkl3_main_1l3_main_2l3_main_3DD E`  l4@4a000000ti,omap4-l4-cfgsimple-bus+ zJcm1@4000 ti,omap4-cm1@ clocks+extalt_clkin_ck fixed-clockD::pad_clks_src_ck fixed-clockpad_clks_ck@108ti,gate-clock&&pad_slimbus_core_clks_ck fixed-clockFFsecure_32k_clk_src_ck fixed-clockslimbus_src_clk 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$,(dpll_core_x2_ckti,omap4-dpll-x2-clockdpll_core_m6x2_ck@140ti,divider-clock@^^dpll_core_m2_ck@130ti,divider-clock0ddrphy_ckfixed-factor-clockdpll_core_m5x2_ck@13cti,divider-clock<div_core_ck@100ti,divider-clockdiv_iva_hs_clk@1dcti,divider-clock div_mpu_hs_clk@19cti,divider-clock dpll_core_m4x2_ck@138ti,divider-clock8dll_clk_div_ckfixed-factor-clockdpll_abe_m2_ck@1f0ti,divider-clock !!dpll_core_m3x2_gate_ck@134 ti,composite-no-wait-gate-clock4dpll_core_m3x2_div_ck@134ti,composite-divider-clock4dpll_core_m3x2_ckti,composite-clockdddpll_core_m7x2_ck@144ti,divider-clockD==iva_hsd_byp_clk_mux_ck@1ac ti,mux-clockdpll_iva_ck@1a0ti,omap4-dpll-clockdpll_iva_x2_ckti,omap4-dpll-x2-clockdpll_iva_m4x2_ck@1b8ti,divider-clockdpll_iva_m5x2_ck@1bcti,divider-clockdpll_mpu_ck@160ti,omap4-dpll-clock`dlhdpll_mpu_m2_ck@170ti,divider-clockpper_hs_clk_div_ckfixed-factor-clock--usb_hs_clk_div_ckfixed-factor-clock33l3_div_ck@100ti,divider-clockl4_div_ck@100ti,divider-clockPPlp_clk_div_ckfixed-factor-clock \\mpu_periphclkfixed-factor-clockocp_abe_iclk@528ti,divider-clock (!per_abe_24m_fclkfixed-factor-clock!DDdmic_sync_mux_ck@538 ti,mux-clock "#$8%%func_dmic_abe_gfclk@538 ti,mux-clock %&'8mcasp_sync_mux_ck@540 ti,mux-clock "#$@((func_mcasp_abe_gfclk@540 ti,mux-clock (&'@mcbsp1_sync_mux_ck@548 ti,mux-clock "#$H))func_mcbsp1_gfclk@548 ti,mux-clock )&'Hmcbsp2_sync_mux_ck@550 ti,mux-clock "#$P**func_mcbsp2_gfclk@550 ti,mux-clock *&'Pmcbsp3_sync_mux_ck@558 ti,mux-clock "#$X++func_mcbsp3_gfclk@558 ti,mux-clock +&'Xslimbus1_fclk_1@560ti,gate-clock$ `slimbus1_fclk_0@560ti,gate-clock"`slimbus1_fclk_2@560ti,gate-clock& `slimbus1_slimbus_clk@560ti,gate-clock' `timer5_sync_mux@568 ti,mux-clock#,htimer6_sync_mux@570 ti,mux-clock#,ptimer7_sync_mux@578 ti,mux-clock#,xtimer8_sync_mux@580 ti,mux-clock#,dummy_ck fixed-clockclockdomainscm2@8000 ti,omap4-cm20clocks+per_hsd_byp_clk_mux_ck@14c ti,mux-clock-L..dpll_per_ck@140ti,omap4-dpll-clock.@DLH//dpll_per_m2_ck@150ti,divider-clock/P77dpll_per_x2_ck@150ti,omap4-dpll-x2-clock/P00dpll_per_m2x2_ck@150ti,divider-clock0P66dpll_per_m3x2_gate_ck@154 ti,composite-no-wait-gate-clock0T11dpll_per_m3x2_div_ck@154ti,composite-divider-clock0T22dpll_per_m3x2_ckti,composite-clock12eedpll_per_m4x2_ck@158ti,divider-clock0X88dpll_per_m5x2_ck@15cti,divider-clock0\;;dpll_per_m6x2_ck@160ti,divider-clock0`55dpll_per_m7x2_ck@164ti,divider-clock0d>>dpll_usb_ck@180ti,omap4-dpll-j-type-clock344dpll_usb_clkdcoldo_ck@1b4ti,fixed-factor-clock4-:dpll_usb_m2_ck@190ti,divider-clock499ducati_clk_mux_ck@100 ti,mux-clock5func_12m_fclkfixed-factor-clock6func_24m_clkfixed-factor-clock7$$func_24mc_fclkfixed-factor-clock6EEfunc_48m_fclk@108ti,divider-clock6!CCfunc_48mc_fclkfixed-factor-clock6<<func_64m_fclk@108ti,divider-clock8!BBfunc_96m_fclk@108ti,divider-clock6!??init_60m_fclk@104ti,divider-clock9!HHper_abe_nc_fclk@108ti,divider-clock!@@aes1_fck@15a0ti,gate-clockaes2_fck@15a8ti,gate-clockdss_sys_clk@1120ti,gate-clock#  dss_tv_clk@1120ti,gate-clock:  dss_dss_clk@1120ti,gate-clock; Hdss_48mhz_clk@1120ti,gate-clock<  fdif_fck@1028ti,divider-clock8( gpio2_dbclk@1460ti,gate-clock,`gpio3_dbclk@1468ti,gate-clock,hgpio4_dbclk@1470ti,gate-clock,pgpio5_dbclk@1478ti,gate-clock,xgpio6_dbclk@1480ti,gate-clock,sgx_clk_mux@1220 ti,mux-clock=> hsi_fck@1338ti,divider-clock68 iss_ctrlclk@1020ti,gate-clock? mcbsp4_sync_mux_ck@14e0 ti,mux-clock?@AAper_mcbsp4_gfclk@14e0 ti,mux-clockA&hsmmc1_fclk@1328 ti,mux-clockB?(hsmmc2_fclk@1330 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pinmux_twl6030_pins^Aomap4_padconf_global@5a0sysconsimple-busp+ zpTTpbias_regulator@60ti,pbias-omap4ti,pbias-omap`Tpbias_mmc_omap4pbias_mmc_omap4w@-l4@300000ti,omap4-l4-wkupsimple-bus+ z0counter@4000ti,omap-counter32k@  kcounter_32kprm@6000 ti,omap4-prm`0 ` clocks+sys_clkin_ck@110 ti,mux-clockUVWXYZ[abe_dpll_bypass_clk_mux_ck@108 ti,mux-clock,  abe_dpll_refclk_mux_ck@10c ti,mux-clock,   dbgclk_mux_ckfixed-factor-clockl4_wkup_clk_mux_ck@108 ti,mux-clock\GGsyc_clk_div_ck@100ti,divider-clock##gpio1_dbclk@1838ti,gate-clock,8dmt1_clk_mux@1840 ti,mux-clock,@usim_ck@1858ti,divider-clock8X!]]usim_fclk@1858ti,gate-clock]Xpmd_stm_clock_mux_ck@1a20 ti,mux-clock ^_ ``pmd_trace_clk_mux_ck@1a20 ti,mux-clock ^_ aastm_clk_div_ck@1a20ti,divider-clock`@  trace_clk_div_div_ck@1a20ti,divider-clocka !bbtrace_clk_div_ckti,clkdm-gate-clockbccbandgap_fclk@1888ti,gate-clock,clockdomainsemu_sys_clkdmti,clockdomaincscrm@a000ti,omap4-scrm clocks+auxclk0_src_gate_ck@310 ti,composite-no-wait-gate-clockdffauxclk0_src_mux_ck@310ti,composite-mux-clock deggauxclk0_src_ckti,composite-clockfghhauxclk0_ck@310ti,divider-clockhxxauxclk1_src_gate_ck@314 ti,composite-no-wait-gate-clockdiiauxclk1_src_mux_ck@314ti,composite-mux-clock dejjauxclk1_src_ckti,composite-clockijkkauxclk1_ck@314ti,divider-clockkyyauxclk2_src_gate_ck@318 ti,composite-no-wait-gate-clockdllauxclk2_src_mux_ck@318ti,composite-mux-clock demmauxclk2_src_ckti,composite-clocklmnnauxclk2_ck@318ti,divider-clocknzzauxclk3_src_gate_ck@31c ti,composite-no-wait-gate-clockdooauxclk3_src_mux_ck@31cti,composite-mux-clock deppauxclk3_src_ckti,composite-clockopqqauxclk3_ck@31cti,divider-clockq{{auxclk4_src_gate_ck@320 ti,composite-no-wait-gate-clockd rrauxclk4_src_mux_ck@320ti,composite-mux-clock de ssauxclk4_src_ckti,composite-clockrsttauxclk4_ck@320ti,divider-clockt ||auxclk5_src_gate_ck@324 ti,composite-no-wait-gate-clockd$uuauxclk5_src_mux_ck@324ti,composite-mux-clock de$vvauxclk5_src_ckti,composite-clockuvwwauxclk5_ck@324ti,divider-clockw$}}auxclkreq0_ck@210 ti,mux-clockxyz{|}auxclkreq1_ck@214 ti,mux-clockxyz{|}auxclkreq2_ck@218 ti,mux-clockxyz{|}auxclkreq3_ck@21c ti,mux-clockxyz{|}auxclkreq4_ck@220 ti,mux-clockxyz{|} auxclkreq5_ck@224 ti,mux-clockxyz{|}$clockdomainspinmux@1e040 ti,omap4-padconfpinctrl-single@8+5 [ypinmux_twl6030_wkup_pinsocmcram@40304000 mmio-sram@0@dma-controller@4a056000ti,omap4430-sdmaJ`0`    ~~gpio@4a310000ti,omap4-gpioJ1 `kgpio1-?O 5gpio@48055000ti,omap4-gpioHP `kgpio2?O 5gpio@48057000ti,omap4-gpioHp `kgpio3?O 5gpio@48059000ti,omap4-gpioH ` kgpio4?O 5gpio@4805b000ti,omap4-gpioH `!kgpio5?O 5gpio@4805d000ti,omap4-gpioH `"kgpio6?O 5elm@48078000ti,am3352-elmH `kelm [disabledgpmc@50000000ti,omap4430-gpmcP+ `b~grxtxq}kgpmcfck 5?Oserial@4806a000ti,omap4-uartH `Hkuart1lserial@4806c000ti,omap4-uartH `Ikuart2lIdefaultserial@48020000ti,omap4-uartH `Jkuart3lJdefaultserial@4806e000ti,omap4-uartH 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compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2i2c3serial0serial1serial2serial3display0display1display2device_typenext-level-cacheregclocksclock-namesclock-latencyoperating-pointscooling-min-levelcooling-max-level#cooling-cellslinux,phandleinterrupt-controller#interrupt-cellscache-unifiedcache-levelinterruptsti,hwmodssramranges#clock-cellsclock-frequencyti,bit-shiftti,max-divti,autoidle-shiftti,index-starts-at-oneti,invert-autoidle-bitclock-multclock-divti,index-power-of-twoti,dividersti,clock-divti,clock-multti,set-rate-parentpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0pinctrl-single,pinssysconregulator-nameregulator-min-microvoltregulator-max-microvolt#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsstatusdmasdma-namesgpmc,num-csgpmc,num-waitpinsti,no-idle-on-initinterrupts-extended#hwlock-cellsregulator-always-onusb-supply#pwm-cells#io-channel-cellsti,audpwron-gpiovio-supplyv2v1-supplyenable-active-highvddvibl-supplyvddvibr-supplyti,vibldrv-resti,vibrdrv-resti,viblmotor-resti,vibrmotor-resti,spi-num-csspi-max-frequencyvdd-supplyti,dual-voltti,needs-special-resetpbias-supplyvmmc-supplybus-widthti,non-removablecap-power-off-cardref-clock-frequencytcxo-clock-frequency#iommu-cellsti,iommu-bus-err-backreg-namesinterrupt-namesti,buffer-sizekeypad,num-rowskeypad,num-columnslinux,keymaplinux,input-no-autorepeatphy-typehw-caps-read-idle-ctrlhw-caps-ll-interfacehw-caps-temp-alertcs1-useddevice-handlectrl-module#phy-cells#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,timer-alwonti,timer-dspti,timer-pwmusb-phyphysphy-namesmultipointnum-epsram-bitsinterface-typemodepowerti,tranxdone-status-maskti,settling-timeti,clock-cyclesti,abb_inforemote-endpointlaneslabelreset-gpiosvdda-supply#thermal-sensor-cellspolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicedensityio-widthtRPab-min-tcktRCD-min-tcktWR-min-tcktRASmin-min-tcktRRD-min-tcktWTR-min-tcktXP-min-tcktRTP-min-tcktCKE-min-tcktCKESR-min-tcktFAW-min-tckmin-freqmax-freqtRPabtRCDtWRtRAS-mintRRDtWTRtXPtRTPtCKESRtDQSCK-maxtFAWtZQCStZQCLtZQinittRAS-max-nstDQSCK-max-deratedregulator-boot-onpwmsmax-brightnessbrightness-levelsdefault-brightness-levelti,modelti,jack-detectionti,mclk-freqti,mcpdmti,dmicti,twl6040ti,audio-routingstartup-delay-us