8؄( L$ti,omap4-pandati,omap4430ti,omap4 +7TI OMAP4 PandaBoardchosenaliases=/ocp/i2c@48070000B/ocp/i2c@48072000G/ocp/i2c@48060000L/ocp/i2c@48350000Q/ocp/serial@4806a000Y/ocp/serial@4806c000a/ocp/serial@48020000i/ocp/serial@4806e000 q/connector0 z/connector1cpus+cpu@0arm,cortex-a9cpucpu  'O 5a cpu@1arm,cortex-a9cpuinterrupt-controller@48241000arm,cortex-a9-gic,H$H$  l2-cache-controller@48242000arm,pl310-cacheH$ =K local-timer@48240600arm,cortex-a9-twd-timerH$  W  interrupt-controller@48281000ti,omap4-wugen-mpu,H(  socti,omap-inframpu ti,omap4-mpubmpuldsp ti,omap3-c64bdspiva ti,ivahdbivaocpti,omap4-l3-nocsimple-bus+qbl3_main_1l3_main_2l3_main_3DD EW  l4@4a000000ti,omap4-l4-cfgsimple-bus+ qJcm1@4000 ti,omap4-cm1@ clocks+extalt_clkin_ckx fixed-clockD ::pad_clks_src_ckx fixed-clock pad_clks_ck@108xti,gate-clock &&pad_slimbus_core_clks_ckx fixed-clock FFsecure_32k_clk_src_ckx fixed-clockslimbus_src_clkx fixed-clock slimbus_clk@108xti,gate-clock  ''sys_32k_ckx fixed-clock ,,virt_12000000_ckx fixed-clock XXvirt_13000000_ckx fixed-clock]@ YYvirt_16800000_ckx fixed-clockY ZZvirt_19200000_ckx fixed-clock$ [[virt_26000000_ckx fixed-clock \\virt_27000000_ckx fixed-clock ]]virt_38400000_ckx fixed-clockI ^^tie_low_clock_ckx fixed-clock bbutmi_phy_clkout_ckx fixed-clock MMxclk60mhsp1_ckx fixed-clock IIxclk60mhsp2_ckx fixed-clock KKxclk60motg_ckx fixed-clock NNdpll_abe_ck@1e0xti,omap4-dpll-m4xen-clock   dpll_abe_x2_ck@1f0xti,omap4-dpll-x2-clock   dpll_abe_m2x2_ck@1f0xti,divider-clock   abe_24m_fclkxfixed-factor-clock  ""abe_clk@108xti,divider-clock  aess_fclk@528xti,divider-clock(  dpll_abe_m3x2_ck@1f4xti,divider-clock  core_hsd_byp_clk_mux_ck@12cx ti,mux-clock, dpll_core_ck@120xti,omap4-dpll-core-clock $,( dpll_core_x2_ckxti,omap4-dpll-x2-clock dpll_core_m6x2_ck@140xti,divider-clock@ aadpll_core_m2_ck@130xti,divider-clock0 ddrphy_ckxfixed-factor-clockdpll_core_m5x2_ck@13cxti,divider-clock< div_core_ck@100xti,divider-clock div_iva_hs_clk@1dcxti,divider-clock div_mpu_hs_clk@19cxti,divider-clock dpll_core_m4x2_ck@138xti,divider-clock8 dll_clk_div_ckxfixed-factor-clockdpll_abe_m2_ck@1f0xti,divider-clock  !!dpll_core_m3x2_gate_ck@134x ti,composite-no-wait-gate-clock4 dpll_core_m3x2_div_ck@134xti,composite-divider-clock4 dpll_core_m3x2_ckxti,composite-clock ggdpll_core_m7x2_ck@144xti,divider-clockD ==iva_hsd_byp_clk_mux_ck@1acx ti,mux-clock dpll_iva_ck@1a0xti,omap4-dpll-clock dpll_iva_x2_ckxti,omap4-dpll-x2-clock dpll_iva_m4x2_ck@1b8xti,divider-clockdpll_iva_m5x2_ck@1bcxti,divider-clockdpll_mpu_ck@160xti,omap4-dpll-clock`dlh dpll_mpu_m2_ck@170xti,divider-clockpper_hs_clk_div_ckxfixed-factor-clock --usb_hs_clk_div_ckxfixed-factor-clock 33l3_div_ck@100xti,divider-clock l4_div_ck@100xti,divider-clock PPlp_clk_div_ckxfixed-factor-clock  __mpu_periphclkxfixed-factor-clock ocp_abe_iclk@528xti,divider-clock (per_abe_24m_fclkxfixed-factor-clock! DDdmic_sync_mux_ck@538x ti,mux-clock "#$8 %%func_dmic_abe_gfclk@538x ti,mux-clock %&'8mcasp_sync_mux_ck@540x ti,mux-clock "#$@ ((func_mcasp_abe_gfclk@540x ti,mux-clock (&'@mcbsp1_sync_mux_ck@548x ti,mux-clock "#$H ))func_mcbsp1_gfclk@548x ti,mux-clock )&'Hmcbsp2_sync_mux_ck@550x ti,mux-clock "#$P **func_mcbsp2_gfclk@550x ti,mux-clock *&'Pmcbsp3_sync_mux_ck@558x ti,mux-clock "#$X ++func_mcbsp3_gfclk@558x ti,mux-clock +&'Xslimbus1_fclk_1@560xti,gate-clock$ `slimbus1_fclk_0@560xti,gate-clock"`slimbus1_fclk_2@560xti,gate-clock& `slimbus1_slimbus_clk@560xti,gate-clock' `timer5_sync_mux@568x ti,mux-clock#,htimer6_sync_mux@570x ti,mux-clock#,ptimer7_sync_mux@578x ti,mux-clock#,xtimer8_sync_mux@580x ti,mux-clock#,dummy_ckx fixed-clockclockdomainscm2@8000 ti,omap4-cm20clocks+per_hsd_byp_clk_mux_ck@14cx ti,mux-clock-L ..dpll_per_ck@140xti,omap4-dpll-clock.@DLH //dpll_per_m2_ck@150xti,divider-clock/P 77dpll_per_x2_ck@150xti,omap4-dpll-x2-clock/P 00dpll_per_m2x2_ck@150xti,divider-clock0P 66dpll_per_m3x2_gate_ck@154x ti,composite-no-wait-gate-clock0T 11dpll_per_m3x2_div_ck@154xti,composite-divider-clock0T 22dpll_per_m3x2_ckxti,composite-clock12 hhdpll_per_m4x2_ck@158xti,divider-clock0X 88dpll_per_m5x2_ck@15cxti,divider-clock0\ ;;dpll_per_m6x2_ck@160xti,divider-clock0` 55dpll_per_m7x2_ck@164xti,divider-clock0d >>dpll_usb_ck@180xti,omap4-dpll-j-type-clock3 44dpll_usb_clkdcoldo_ck@1b4xti,fixed-factor-clock4$1dpll_usb_m2_ck@190xti,divider-clock4 99ducati_clk_mux_ck@100x ti,mux-clock5func_12m_fclkxfixed-factor-clock6func_24m_clkxfixed-factor-clock7 $$func_24mc_fclkxfixed-factor-clock6 EEfunc_48m_fclk@108xti,divider-clock6 CCfunc_48mc_fclkxfixed-factor-clock6 <<func_64m_fclk@108xti,divider-clock8 BBfunc_96m_fclk@108xti,divider-clock6 ??init_60m_fclk@104xti,divider-clock9 HHper_abe_nc_fclk@108xti,divider-clock! @@aes1_fck@15a0xti,gate-clockaes2_fck@15a8xti,gate-clockdss_sys_clk@1120xti,gate-clock#   dss_tv_clk@1120xti,gate-clock:   dss_dss_clk@1120xti,gate-clock; ? dss_48mhz_clk@1120xti,gate-clock<   fdif_fck@1028xti,divider-clock8(gpio2_dbclk@1460xti,gate-clock,`gpio3_dbclk@1468xti,gate-clock,hgpio4_dbclk@1470xti,gate-clock,pgpio5_dbclk@1478xti,gate-clock,xgpio6_dbclk@1480xti,gate-clock,sgx_clk_mux@1220x ti,mux-clock=> hsi_fck@1338xti,divider-clock68iss_ctrlclk@1020xti,gate-clock? mcbsp4_sync_mux_ck@14e0x ti,mux-clock?@ AAper_mcbsp4_gfclk@14e0x ti,mux-clockA&hsmmc1_fclk@1328x ti,mux-clockB?(hsmmc2_fclk@1330x ti,mux-clockB?0ocp2scp_usb_phy_phy_48m@13e0xti,gate-clockCsha2md5_fck@15c8xti,gate-clockslimbus2_fclk_1@1538xti,gate-clockD 8slimbus2_fclk_0@1538xti,gate-clockE8slimbus2_slimbus_clk@1538xti,gate-clockF 8smartreflex_core_fck@638xti,gate-clockG8smartreflex_iva_fck@630xti,gate-clockG0smartreflex_mpu_fck@628xti,gate-clockG(cm2_dm10_mux@1428x ti,mux-clock,(cm2_dm11_mux@1430x ti,mux-clock,0cm2_dm2_mux@1438x ti,mux-clock,8cm2_dm3_mux@1440x ti,mux-clock,@cm2_dm4_mux@1448x ti,mux-clock,Hcm2_dm9_mux@1450x ti,mux-clock,Pusb_host_fs_fck@13d0xti,gate-clock< QQutmi_p1_gfclk@1358x ti,mux-clockHIX JJusb_host_hs_utmi_p1_clk@1358xti,gate-clockJXutmi_p2_gfclk@1358x ti,mux-clockHKX LLusb_host_hs_utmi_p2_clk@1358xti,gate-clockL Xusb_host_hs_utmi_p3_clk@1358xti,gate-clockH Xusb_host_hs_hsic480m_p1_clk@1358xti,gate-clock9 Xusb_host_hs_hsic60m_p1_clk@1358xti,gate-clockH Xusb_host_hs_hsic60m_p2_clk@1358xti,gate-clockH Xusb_host_hs_hsic480m_p2_clk@1358xti,gate-clock9Xusb_host_hs_func48mclk@1358xti,gate-clock<Xusb_host_hs_fck@1358xti,gate-clockHXotg_60m_gfclk@1360x ti,mux-clockMN` OOusb_otg_hs_xclk@1360xti,gate-clockO`usb_otg_hs_ick@1360xti,gate-clock`usb_phy_cm_clk32k@640xti,gate-clock,@ usb_tll_hs_usb_ch2_clk@1368xti,gate-clockH husb_tll_hs_usb_ch0_clk@1368xti,gate-clockHhusb_tll_hs_usb_ch1_clk@1368xti,gate-clockH husb_tll_hs_ick@1368xti,gate-clockPhclockdomainsl3_init_clkdmti,clockdomain4Qscm@2000ti,omap4-scm-coresimple-bus + q scm_conf@0syscon+scm@100000%ti,omap4-scm-padconf-coresimple-bus+ qpinmux@40 ti,omap4-padconfpinctrl-single@+,RpdefaultRSTUV pinmux_twl6040_pins` pinmux_mcpdm_pins( pinmux_mcbsp1_pins  pinmux_dss_dpi_pins"$&(*,.0246tvxz|~ RRpinmux_tfp410_pinsD SSpinmux_dss_hdmi_pinsZ\^ TTpinmux_tpd12s015_pins"HX  UUpinmux_hsusbb1_pins`            VVpinmux_i2c1_pins pinmux_i2c2_pins pinmux_i2c3_pins pinmux_i2c4_pins pinmux_wl12xx_gpio &,02 pinmux_wl12xx_pins@8:   pinmux_twl6030_pins^A omap4_padconf_global@5a0sysconsimple-busp+ qp WWpbias_regulator@60ti,pbias-omap4ti,pbias-omap`Wpbias_mmc_omap4pbias_mmc_omap4w@- l4@300000ti,omap4-l4-wkupsimple-bus+ q0counter@4000ti,omap-counter32k@  bcounter_32kprm@6000 ti,omap4-prm`0 W clocks+sys_clkin_ck@110x ti,mux-clockXYZ[\]^ abe_dpll_bypass_clk_mux_ck@108x ti,mux-clock,  abe_dpll_refclk_mux_ck@10cx ti,mux-clock,   dbgclk_mux_ckxfixed-factor-clockl4_wkup_clk_mux_ck@108x ti,mux-clock_ GGsyc_clk_div_ck@100xti,divider-clock ##gpio1_dbclk@1838xti,gate-clock,8dmt1_clk_mux@1840x ti,mux-clock,@usim_ck@1858xti,divider-clock8X ``usim_fclk@1858xti,gate-clock`Xpmd_stm_clock_mux_ck@1a20x ti,mux-clock ab  ccpmd_trace_clk_mux_ck@1a20x ti,mux-clock ab  ddstm_clk_div_ck@1a20xti,divider-clockc@ trace_clk_div_div_ck@1a20xti,divider-clockd  eetrace_clk_div_ckxti,clkdm-gate-clocke ffbandgap_fclk@1888xti,gate-clock,clockdomainsemu_sys_clkdmti,clockdomainfscrm@a000ti,omap4-scrm clocks+auxclk0_src_gate_ck@310x ti,composite-no-wait-gate-clockg iiauxclk0_src_mux_ck@310xti,composite-mux-clock gh jjauxclk0_src_ckxti,composite-clockij kkauxclk0_ck@310xti,divider-clockk {{auxclk1_src_gate_ck@314x ti,composite-no-wait-gate-clockg llauxclk1_src_mux_ck@314xti,composite-mux-clock gh mmauxclk1_src_ckxti,composite-clocklm nnauxclk1_ck@314xti,divider-clockn ||auxclk2_src_gate_ck@318x ti,composite-no-wait-gate-clockg ooauxclk2_src_mux_ck@318xti,composite-mux-clock gh ppauxclk2_src_ckxti,composite-clockop qqauxclk2_ck@318xti,divider-clockq }}auxclk3_src_gate_ck@31cx ti,composite-no-wait-gate-clockg rrauxclk3_src_mux_ck@31cxti,composite-mux-clock gh ssauxclk3_src_ckxti,composite-clockrs ttauxclk3_ck@31cxti,divider-clockt ~~auxclk4_src_gate_ck@320x ti,composite-no-wait-gate-clockg  uuauxclk4_src_mux_ck@320xti,composite-mux-clock gh  vvauxclk4_src_ckxti,composite-clockuv wwauxclk4_ck@320xti,divider-clockw  auxclk5_src_gate_ck@324x ti,composite-no-wait-gate-clockg$ xxauxclk5_src_mux_ck@324xti,composite-mux-clock gh$ yyauxclk5_src_ckxti,composite-clockxy zzauxclk5_ck@324xti,divider-clockz$ auxclkreq0_ck@210x ti,mux-clock{|}~auxclkreq1_ck@214x ti,mux-clock{|}~auxclkreq2_ck@218x ti,mux-clock{|}~auxclkreq3_ck@21cx ti,mux-clock{|}~auxclkreq4_ck@220x ti,mux-clock{|}~ auxclkreq5_ck@224x ti,mux-clock{|}~$clockdomainspinmux@1e040 ti,omap4-padconfpinctrl-single@8+,Rppinmux_leds_wkpins pinmux_twl6030_wkup_pins ocmcram@40304000 mmio-sram@0@ dma-controller@4a056000ti,omap4430-sdmaJ`0W    gpio@4a310000ti,omap4-gpioJ1 Wbgpio1$6F, gpio@48055000ti,omap4-gpioHP Wbgpio26F, gpio@48057000ti,omap4-gpioHp Wbgpio36F,gpio@48059000ti,omap4-gpioH W bgpio46F, gpio@4805b000ti,omap4-gpioH W!bgpio56F,gpio@4805d000ti,omap4-gpioH W"bgpio66F,elm@48078000ti,am3352-elmH Wbelm Rdisabledgpmc@50000000ti,omap4430-gpmcP+ WY^rxtxhtbgpmcfck,6Fserial@4806a000ti,omap4-uartH WHbuart1lserial@4806c000ti,omap4-uartH WIbuart2lIserial@48020000ti,omap4-uartH WJbuart3lJserial@4806e000ti,omap4-uartH WFbuart4lFspinlock@4a0f6000ti,omap4-hwspinlockJ` bspinlocki2c@48070000 ti,omap4-i2cH W8+bi2c1defaulttwl@48H W ti,twl6030,defaultrtcti,twl4030-rtcW regulator-vaux1ti,twl6030-vaux1B@-regulator-vaux2ti,twl6030-vaux2O*regulator-vaux3ti,twl6030-vaux3B@-regulator-vmmcti,twl6030-vmmcO- regulator-vppti,twl6030-vppw@&%regulator-vusimti,twl6030-vusimO,@ regulator-vdacti,twl6030-vdac regulator-vanati,twl6030-vanaregulator-vcxioti,twl6030-vcxio regulator-vusbti,twl6030-vusb regulator-v1v8ti,twl6030-v1v8 regulator-v2v1ti,twl6030-v2v1 usb-comparatorti,twl6030-usbW pwmti,twl6030-pwmpwmledti,twl6030-pwmledgpadcti,twl6030-gpadcWtwl@4b ti,twl6040xKdefault Ww  i2c@48072000 ti,omap4-i2cH  W9+bi2c2defaulti2c@48060000 ti,omap4-i2cH W=+bi2c3default eeprom@50 ti,eepromPi2c@48350000 ti,omap4-i2cH5 W>+bi2c4defaultspi@48098000ti,omap4-mcspiH  WA+bmcspi12@Y#$%&'()* ^tx0rx0tx1rx1tx2rx2tx3rx3spi@4809a000ti,omap4-mcspiH  WB+bmcspi22 Y+,-.^tx0rx0tx1rx1spi@480b8000ti,omap4-mcspiH  W[+bmcspi32Y^tx0rx0spi@480ba000ti,omap4-mcspiH  W0+bmcspi42YFG^tx0rx0mmc@4809c000ti,omap4-hsmmcH  WSbmmc1@MY=>^txrxdq}mmc@480b4000ti,omap4-hsmmcH @ WVbmmc2MY/0^txrx Rdisabledmmc@480ad000ti,omap4-hsmmcH  W^bmmc3MYMN^txrx Rdisabledmmc@480d1000ti,omap4-hsmmcH  W`bmmc4MY9:^txrx Rdisabledmmc@480d5000ti,omap4-hsmmcH P W;bmmc5MY;<^txrxdefaultq;}+wlcore@2 ti,wl1271 WImmu@4a066000ti,omap4-iommuJ` Wbmmu_dspmmu@55082000ti,omap4-iommuU  Wdbmmu_ipuwdt@4a314000ti,omap4-wdtti,omap3-wdtJ1@ WP bwd_timer2mcpdm@40132000ti,omap4-mcpdm@ I mpudma WpbmcpdmYAB^up_linkdn_linkRokaydefaultpdmclk dmic@4012e000ti,omap4-dmic@Impudma WrbdmicYC^up_link Rdisabledmcbsp@40122000ti,omap4-mcbsp@ I mpudma Wcommonbmcbsp1Y!"^txrxRokaydefaultmcbsp@40124000ti,omap4-mcbsp@@I@mpudma Wcommonbmcbsp2Y^txrx Rdisabledmcbsp@40126000ti,omap4-mcbsp@`I`mpudma Wcommonbmcbsp3Y^txrx Rdisabledmcbsp@48096000ti,omap4-mcbspH `mpu Wcommonbmcbsp4Y ^txrx Rdisabledkeypad@4a31c000ti,omap4-keypadJ1 Wxmpubkbddmm@4e000000 ti,omap4-dmmN Wqbdmmemif@4c000000 ti,emif-4dL Wnbemif1(=PYemif@4d000000 ti,emif-4dM Wobemif2(=PYocp2scp@4a0ad000ti,omap-ocp2scpJ +qbocp2scp_usb_phyusb2phy@4a0ad080 ti,omap-usb2J ЀXgwkupclks mailbox@4a0f4000ti,omap4-mailboxJ@ Wbmailbox~mbox_ipu  mbox_dsp  timer@4a318000ti,omap3430-timerJ1 W%btimer1timer@48032000ti,omap3430-timerH  W&btimer2timer@48034000ti,omap4430-timerH@ W'btimer3timer@48036000ti,omap4430-timerH` W(btimer4timer@40138000ti,omap4430-timer@I W)btimer5timer@4013a000ti,omap4430-timer@I W*btimer6timer@4013c000ti,omap4430-timer@I W+btimer7timer@4013e000ti,omap4430-timer@I W,btimer8timer@4803e000ti,omap4430-timerH W-btimer9timer@48086000ti,omap3430-timerH` W.btimer10timer@48088000ti,omap4430-timerH W/btimer11usbhstll@4a062000 ti,usbhs-tllJ  WN busb_tll_hsusbhshost@4a064000ti,usbhs-hostJ@ busb_host_hs+q HIK3refclk_60m_intrefclk_60m_ext_p1refclk_60m_ext_p2 ehci-phyohci@4a064800ti,ohci-omap3JH  WLehci@4a064c00 ti,ehci-omapJL  WMcontrol-phy@4a002300ti,control-phy-usb2J#power control-phy@4a00233cti,control-phy-otghsJ#<otghs_control usb_otg_hs@4a0ab000ti,omap4-musbJ W\]mcdma busb_otg_hs usb2-phy" g+:2aes@4b501000 ti,omap4-aesbaesKP WUYon^txrxdes@480a5000 ti,omap4-desbdesH P WRYut^txrxregulator-abb-mpu ti,abb-v2abb_mpu+@Y2jRokayJ0{J0`base-addressint-addressxzO1regulator-abb-iva ti,abb-v2abb_iva+@Y2j RdisabledJ0{J0`base-addressint-addressdss@58000000 ti,omap4-dssXRok bdss_corefck+qdispc@58001000ti,omap4-dispcX W bdss_dispcfckencoder@58002000ti,omap4-rfbiX  Rdisabled bdss_rfbifckickencoder@58003000ti,omap4-vencX0 Rdisabled bdss_vencfckencoder@58004000 ti,omap4-dsiX@XB@XC protophypll W5 Rdisabled bdss_dsi1 fcksys_clkencoder@58005000 ti,omap4-dsiXPXR@XS protophypll WTRok bdss_dsi2 fcksys_clkencoder@58006000ti,omap4-hdmi X`XbXcXdwppllphycore WeRok bdss_hdmi fcksys_clkYL ^audio_txportendpoint portendpoint bandgap@4a002260J"`J#,ti,omap4430-bandgap thermal-zonescpu_thermaltripscpu_alertpassive cpu_critH criticalcooling-mapsmap0 lpddr2#Elpida,ECB240ABACNjedec,lpddr2-s4-5 >LYeu lpddr2-timings@0jedec,lpddr2-timingsׄRFP:'LL L:| P%_+~@1B@9pEplpddr2-timings@1jedec,lpddr2-timings RFP:''L L:| P%_+~@1B@9pEpmemory@80000000memory@leds gpio-ledsdefaultheartbeatXpandaboard::status1 ^ dheartbeatmmcXpandaboard::status2 ^dmmc0soundti,abe-twl6040 zPandaBoardIHeadset StereophoneHSOLHeadset StereophoneHSORExt SpkHFLExt SpkHFRLine OutAUXLLine OutAUXRHSMICHeadset MicHeadset MicHeadset Mic BiasAFMLLine InAFMRLine Inhsusb1_power_regregulator-fixed hsusb1_vbus2Z2Z p hsusb1_phyusb-nop-xceiv ~ main_clk$ wl12xx_vmmcdefaultregulator-fixedvwl1271w@w@  p encoder0 ti,tfp410 ports+port@0endpoint port@1endpoint connector0dvi-connectorXdvi portendpoint encoder1 ti,tpd12s015$^ ports+port@0endpoint port@1endpoint connector1hdmi-connectorXhdmiaportendpoint  compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2i2c3serial0serial1serial2serial3display0display1device_typenext-level-cacheregclocksclock-namesclock-latencyoperating-pointscooling-min-levelcooling-max-level#cooling-cellslinux,phandleinterrupt-controller#interrupt-cellscache-unifiedcache-levelinterruptsti,hwmodssramranges#clock-cellsclock-frequencyti,bit-shiftti,max-divti,autoidle-shiftti,index-starts-at-oneti,invert-autoidle-bitclock-multclock-divti,index-power-of-twoti,dividersti,clock-divti,clock-multti,set-rate-parentpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0pinctrl-single,pinssysconregulator-nameregulator-min-microvoltregulator-max-microvolt#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsstatusdmasdma-namesgpmc,num-csgpmc,num-waitpinsti,no-idle-on-initinterrupts-extended#hwlock-cellsregulator-always-onusb-supply#pwm-cells#io-channel-cellsti,audpwron-gpiovio-supplyv2v1-supplyenable-active-highti,spi-num-csti,dual-voltti,needs-special-resetpbias-supplyvmmc-supplybus-widthnon-removablecap-power-off-cardref-clock-frequency#iommu-cellsti,iommu-bus-err-backreg-namesinterrupt-namesti,buffer-sizephy-typehw-caps-read-idle-ctrlhw-caps-ll-interfacehw-caps-temp-alertcs1-useddevice-handlectrl-module#phy-cells#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,timer-alwonti,timer-dspti,timer-pwmport1-modephysusb-phyphy-namesmultipointnum-epsram-bitsinterface-typepowerti,tranxdone-status-maskti,settling-timeti,clock-cyclesti,abb_infovdd-supplyvdda-supplyremote-endpointdata-lines#thermal-sensor-cellspolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicedensityio-widthtRPab-min-tcktRCD-min-tcktWR-min-tcktRASmin-min-tcktRRD-min-tcktWTR-min-tcktXP-min-tcktRTP-min-tcktCKE-min-tcktCKESR-min-tcktFAW-min-tckmin-freqmax-freqtRPabtRCDtWRtRAS-mintRRDtWTRtXPtRTPtCKESRtDQSCK-maxtFAWtZQCStZQCLtZQinittRAS-max-nstDQSCK-max-deratedlabelgpioslinux,default-triggerti,modelti,mclk-freqti,mcpdmti,twl6040ti,audio-routingstartup-delay-usregulator-boot-onreset-gpiosvcc-supplypowerdown-gpiosdigitalddc-i2c-bus