8( 2Fgumstix,omap3-overo-gallop43gumstix,omap3-overoti,omap36xxti,omap3 +17OMAP36xx/AM37xx/DM37xx Gumstix Overo on Gallop43chosenaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/serial@4806a000T/ocp@68000000/serial@4806c000\/ocp@68000000/serial@49020000d/ocp@68000000/serial@49042000 l/displaycpus+cpu@0arm,cortex-a8ucpucpus 'O 57pmu@54000000arm,cortex-a8-pmuTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-bush +l3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-bus + pinmux@30 ti,omap3-padconfpinctrl-single08+4defaultBLRpinmux_uart2_pins Z<>@BLRpinmux_i2c1_pinsZLRpinmux_mmc1_pins0ZLRpinmux_mmc2_pins0Z(*,.02LRpinmux_w3cbw003c_pinsZlLRpinmux_hsusb2_pins@Z      LRpinmux_twl4030_pinsZALRpinmux_i2c3_pinsZLRpinmux_uart3_pinsZnpLRpinmux_dss_dpi_pinsZLRpinmux_lte430_pinsZDLRpinmux_backlight_pinsZFLRpinmux_mcspi1_pins ZLRpinmux_ads7846_pinsZ LRscm_conf@270sysconsimple-busp0+ p0LRpbias_regulator@2b0ti,pbias-omap3ti,pbias-omapnpbias_mmc_omap2430upbias_mmc_omap2430w@-LRclocks+mcbsp5_mux_fck@68ti,composite-mux-clockhLRmcbsp5_fckti,composite-clockLRmcbsp1_mux_fck@4ti,composite-mux-clockL R mcbsp1_fckti,composite-clock LRmcbsp2_mux_fck@4ti,composite-mux-clock L R mcbsp2_fckti,composite-clock LRmcbsp3_mux_fck@68ti,composite-mux-clock hLRmcbsp3_fckti,composite-clockLRmcbsp4_mux_fck@68ti,composite-mux-clock hLRmcbsp4_fckti,composite-clockLRclockdomainspinmux@a00 ti,omap3-padconfpinctrl-single \+pinmux_twl4030_vpins ZLRaes@480c5000 ti,omap3-aesaesH PPABtxrxprm@48306000 ti,omap3-prmH0`@ clocks+virt_16_8m_ck fixed-clockYLRosc_sys_ck@d40 ti,mux-clock @LRsys_ck@1270ti,divider-clockpLRsys_clkout1@d70ti,gate-clock pdpll3_x2_ckfixed-factor-clockdpll3_m2x2_ckfixed-factor-clockLRdpll4_x2_ckfixed-factor-clockcorex2_fckfixed-factor-clockLRwkup_l4_ickfixed-factor-clockLNRNcorex2_d3_fckfixed-factor-clockLRcorex2_d5_fckfixed-factor-clockLRclockdomainscm@48004000 ti,omap3-cmH@@clocks+dummy_apb_pclk fixed-clockomap_32k_fck fixed-clockL@R@virt_12m_ck fixed-clockLRvirt_13m_ck fixed-clock]@LRvirt_19200000_ck fixed-clock$LRvirt_26000000_ck fixed-clockLRvirt_38_4m_ck fixed-clockILRdpll4_ck@d00ti,omap3-dpll-per-j-type-clock D 0LRdpll4_m2_ck@d48ti,divider-clock? HL R dpll4_m2x2_mul_ckfixed-factor-clock L!R!dpll4_m2x2_ck@d00ti,hsdiv-gate-clock! $L"R"omap_96m_alwon_fckfixed-factor-clock"L)R)dpll3_ck@d00ti,omap3-dpll-core-clock @ 0LRdpll3_m3_ck@1140ti,divider-clock@L#R#dpll3_m3x2_mul_ckfixed-factor-clock#L$R$dpll3_m3x2_ck@d00ti,hsdiv-gate-clock$  $L%R%emu_core_alwon_ckfixed-factor-clock%LbRbsys_altclk fixed-clockL.R.mcbsp_clks fixed-clockLRdpll3_m2_ck@d40ti,divider-clock @LRcore_ckfixed-factor-clockL&R&dpll1_fck@940ti,divider-clock& @L'R'dpll1_ck@904ti,omap3-dpll-clock'  $ @ 4LRdpll1_x2_ckfixed-factor-clockL(R(dpll1_x2m2_ck@944ti,divider-clock( DL<R<cm_96m_fckfixed-factor-clock)L*R*omap_96m_fck@d40 ti,mux-clock* @LEREdpll4_m3_ck@e40ti,divider-clock @L+R+dpll4_m3x2_mul_ckfixed-factor-clock+L,R,dpll4_m3x2_ck@d00ti,hsdiv-gate-clock, $L-R-omap_54m_fck@d40 ti,mux-clock-. @L8R8cm_96m_d2_fckfixed-factor-clock*L/R/omap_48m_fck@d40 ti,mux-clock/. @L0R0omap_12m_fckfixed-factor-clock0LGRGdpll4_m4_ck@e40ti,divider-clock @L1R1dpll4_m4x2_mul_ckti,fixed-factor-clock1:HUL2R2dpll4_m4x2_ck@d00ti,gate-clock2 $ULRdpll4_m5_ck@f40ti,divider-clock?@L3R3dpll4_m5x2_mul_ckti,fixed-factor-clock3:HUL4R4dpll4_m5x2_ck@d00ti,hsdiv-gate-clock4 $ULjRjdpll4_m6_ck@1140ti,divider-clock?@L5R5dpll4_m6x2_mul_ckfixed-factor-clock5L6R6dpll4_m6x2_ck@d00ti,hsdiv-gate-clock6 $L7R7emu_per_alwon_ckfixed-factor-clock7LcRcclkout2_src_gate_ck@d70 ti,composite-no-wait-gate-clock& pL9R9clkout2_src_mux_ck@d70ti,composite-mux-clock&*8 pL:R:clkout2_src_ckti,composite-clock9:L;R;sys_clkout2@d70ti,divider-clock;@ phmpu_ckfixed-factor-clock<L=R=arm_fck@924ti,divider-clock= $emu_mpu_alwon_ckfixed-factor-clock=LdRdl3_ick@a40ti,divider-clock& @L>R>l4_ick@a40ti,divider-clock> @L?R?rm_ick@c40ti,divider-clock? @gpt10_gate_fck@a00ti,composite-gate-clock  LARAgpt10_mux_fck@a40ti,composite-mux-clock@ @LBRBgpt10_fckti,composite-clockABgpt11_gate_fck@a00ti,composite-gate-clock  LCRCgpt11_mux_fck@a40ti,composite-mux-clock@ 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LRgpio1_ick@c10ti,omap3-interface-clockN LRomap_32ksync_ick@c10ti,omap3-interface-clockN LRgpt12_ick@c10ti,omap3-interface-clockN LRgpt1_ick@c10ti,omap3-interface-clockN LRper_96m_fckfixed-factor-clock)L R per_48m_fckfixed-factor-clock0LOROuart3_fck@1000ti,wait-gate-clockO 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L^R^gpt9_mux_fck@1040ti,composite-mux-clock@@L_R_gpt9_fckti,composite-clock^_per_32k_alwon_fckfixed-factor-clock@L`R`gpio6_dbck@1000ti,gate-clock`LRgpio5_dbck@1000ti,gate-clock`LRgpio4_dbck@1000ti,gate-clock`LRgpio3_dbck@1000ti,gate-clock`LRgpio2_dbck@1000ti,gate-clock` LRwdt3_fck@1000ti,wait-gate-clock` LRper_l4_ickfixed-factor-clock?LaRagpio6_ick@1010ti,omap3-interface-clockaLRgpio5_ick@1010ti,omap3-interface-clockaLRgpio4_ick@1010ti,omap3-interface-clockaLRgpio3_ick@1010ti,omap3-interface-clockaLRgpio2_ick@1010ti,omap3-interface-clocka LRwdt3_ick@1010ti,omap3-interface-clocka LRuart3_ick@1010ti,omap3-interface-clocka LRuart4_ick@1010ti,omap3-interface-clockaLRgpt9_ick@1010ti,omap3-interface-clocka LRgpt8_ick@1010ti,omap3-interface-clocka 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compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2serial0serial1serial2serial3display0device_typeregclocksclock-namesclock-latencyoperating-pointsinterruptsti,hwmodsranges#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0linux,phandlepinctrl-single,pinssysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividers#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedbci3v1-supplyregulator-always-onti,use-ledsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columns#io-channel-cellsstatuspagesizeVdd-supplyVdd_IO-supplyst,click-single-xst,click-single-yst,click-single-zst,click-thresh-xst,click-thresh-yst,click-thresh-zst,irq1-clickst,irq2-clickst,wakeup-x-lost,wakeup-x-hist,wakeup-y-lost,wakeup-y-hist,wakeup-z-lost,wakeup-z-hist,min-limit-xst,min-limit-yst,min-limit-zst,max-limit-xst,max-limit-yst,max-limit-z#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csvcc-supplyspi-max-frequencypendown-gpioti,x-minti,x-maxti,y-minti,y-maxti,x-plate-ohmsti,pressure-maxwakeup-sourceti,dual-voltpbias-supplyvmmc-supplybus-widthvqmmc-supplyvmmc_aux-supplycap-sdio-irqnon-removable#iommu-cellsti,#tlb-entriesreg-namesinterrupt-namesti,buffer-sizeti,timer-alwonti,timer-dspti,timer-pwmti,timer-secureport2-modephysgpmc,num-csgpmc,num-waitpinslinux,mtd-namenand-bus-widthgpmc,device-widthti,nand-ecc-optgpmc,sync-clk-psgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,we-off-nsgpmc,oe-off-nsgpmc,access-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,wr-access-nsgpmc,wr-data-mux-bus-nslabelmultipointnum-epsram-bitsinterface-typeusb-phyphy-namespowerremote-endpointdata-linesti,tranxdone-status-maskti,settling-timeti,clock-cyclesti,abb_infoiommusti,phy-type#thermal-sensor-cellspwmsmax-brightnesslinux,default-triggerti,modelti,mcbspstartup-delay-usenable-active-highreset-gpiosenable-gpioshactivevactivehfront-porchhback-porchhsync-lenvback-porchvfront-porchvsync-lenhsync-activevsync-activede-activepixelclk-activedefault-onlinux,code