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ti,composite-no-wait-gate-clockt-p p[@a@clkout2_src_mux_ck@d70ti,composite-mux-clockt-%1?p p[AaAclkout2_src_ckti,composite-clockt@A[BaBsys_clkout2@d70ti,divider-clocktB@p pjmpu_ckfixed-factor-clocktC[DaDarm_fck@924ti,divider-clocktDp $emu_mpu_alwon_ckfixed-factor-clocktD[kakl3_ick@a40ti,divider-clockt-p @[EaEl4_ick@a40ti,divider-clocktEp @[FaFrm_ick@c40ti,divider-clocktFp @gpt10_gate_fck@a00ti,composite-gate-clockt% p [HaHgpt10_mux_fck@a40ti,composite-mux-clocktG%p @[IaIgpt10_fckti,composite-clocktHIgpt11_gate_fck@a00ti,composite-gate-clockt% p [JaJgpt11_mux_fck@a40ti,composite-mux-clocktG%p @[KaKgpt11_fckti,composite-clocktJKcore_96m_fckfixed-factor-clocktL[ a mmchs2_fck@a00ti,wait-gate-clockt p [ammchs1_fck@a00ti,wait-gate-clockt p [ai2c3_fck@a00ti,wait-gate-clockt p [ai2c2_fck@a00ti,wait-gate-clockt p [ai2c1_fck@a00ti,wait-gate-clockt p [amcbsp5_gate_fck@a00ti,composite-gate-clockt  p [amcbsp1_gate_fck@a00ti,composite-gate-clockt  p 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[aper_96m_fckfixed-factor-clockt0[aper_48m_fckfixed-factor-clockt7[VaVuart3_fck@1000ti,wait-gate-clocktVp [agpt2_gate_fck@1000ti,composite-gate-clockt%p[WaWgpt2_mux_fck@1040ti,composite-mux-clocktG%p@[XaXgpt2_fckti,composite-clocktWXgpt3_gate_fck@1000ti,composite-gate-clockt%p[YaYgpt3_mux_fck@1040ti,composite-mux-clocktG%p@[ZaZgpt3_fckti,composite-clocktYZgpt4_gate_fck@1000ti,composite-gate-clockt%p[[a[gpt4_mux_fck@1040ti,composite-mux-clocktG%p@[\a\gpt4_fckti,composite-clockt[\gpt5_gate_fck@1000ti,composite-gate-clockt%p[]a]gpt5_mux_fck@1040ti,composite-mux-clocktG%p@[^a^gpt5_fckti,composite-clockt]^gpt6_gate_fck@1000ti,composite-gate-clockt%p[_a_gpt6_mux_fck@1040ti,composite-mux-clocktG%p@[`a`gpt6_fckti,composite-clockt_`gpt7_gate_fck@1000ti,composite-gate-clockt%p[aaagpt7_mux_fck@1040ti,composite-mux-clocktG%p@[babgpt7_fckti,composite-clocktabgpt8_gate_fck@1000ti,composite-gate-clockt% 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compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2serial0serial1serial2device_typeregclocksclock-namesclock-latencyoperating-pointscpu0-supplyinterruptsti,hwmodsranges#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0pinctrl-single,pinslinux,phandlesysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftdmasdma-namesstatusclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividers#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedbci3v1-supplyregulator-always-onti,use-ledsti,pullupsti,pulldownsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columns#io-channel-cells#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csspi-max-frequencyspi-cphati,dual-voltpbias-supplyvmmc-supplyvmmc_aux-supplycd-gpiosbus-widthnon-removablecap-power-off-card#iommu-cellsti,#tlb-entriesreg-namesinterrupt-namesti,buffer-sizeti,timer-alwonti,timer-dspti,timer-pwmti,timer-secureport2-modephysgpmc,num-csgpmc,num-waitpinsnand-bus-widthgpmc,device-widthti,nand-ecc-optgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,oe-on-nsgpmc,oe-off-nsgpmc,we-on-nsgpmc,we-off-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,access-nsgpmc,wr-access-nslabelmultipointnum-epsram-bitsinterface-typeusb-phyphy-namespoweriommusti,phy-type#thermal-sensor-cellsgpiostartup-delay-usreset-gpiosvcc-supplyti,modelti,mcbspenable-active-low