q8h( 0Iheadacoustics,omap3-ha-lcdtechnexion,omap3-tao3530ti,omap34xxti,omap3 +77TI OMAP3 HEAD acoustics LCD-baseboard with TAO3530 SOMchosenaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/serial@4806a000T/ocp@68000000/serial@4806c000\/ocp@68000000/serial@49020000 d/displaycpus+cpu@0arm,cortex-a8mcpuy}cpu(HАg8 Odp` 'ppmu@54000000arm,cortex-a8-pmuyTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-busyh +l3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-busy + pinmux@30 ti,omap3-padconfpinctrl-singley08+8default F pinmux_hsusbb2_pins`P          djpinmux_mmc1_pinsPP "$&djpinmux_mmc2_pins0P(*,.02djpinmux_wlan_gpioP^pinmux_uart3_pinsPnApdjpinmux_i2c3_pinsPdjpinmux_mcspi1_pins Pdjpinmux_mcspi3_pins Pdjpinmux_mcbsp3_pins P<>@Bdjpinmux_twl4030_pinsPAdjpinmux_sound2_pinsPnpinmux_led_blue_pinsPdjpinmux_led_green_pinsPd j pinmux_led_red_pinsPd j pinmux_poweroff_pinsPd j pinmux_powerdown_input_pinsPdjfpga_boot0_pins Pdjfpga_boot1_pins Prtvxdjpinmux_touchscreen_irq_pinsP4pinmux_touchscreen_wake_pinsPd j pinmux_dss_dpi_pinsPdjpinmux_lte430_pinsP8djpinmux_backlight_pinsP:djscm_conf@270sysconsimple-busyp0+ p0d j pbias_regulator@2b0ti,pbias-omap3ti,pbias-omapyr pbias_mmc_omap2430ypbias_mmc_omap2430w@-djclocks+mcbsp5_mux_fck@68ti,composite-mux-clock} yhdjmcbsp5_fckti,composite-clock}djmcbsp1_mux_fck@4ti,composite-mux-clock} ydjmcbsp1_fckti,composite-clock}djmcbsp2_mux_fck@4ti,composite-mux-clock}ydjmcbsp2_fckti,composite-clock}djmcbsp3_mux_fck@68ti,composite-mux-clock}yhdjmcbsp3_fckti,composite-clock}djmcbsp4_mux_fck@68ti,composite-mux-clock}yhdjmcbsp4_fckti,composite-clock}djclockdomainspinmux@a00 ti,omap3-padconfpinctrl-singley \+pinmux_twl4030_vpins Pdjaes@480c5000 ti,omap3-aesaesyH PPABtxrx disabledprm@48306000 ti,omap3-prmyH0`@ clocks+virt_16_8m_ck fixed-clockYd j osc_sys_ck@d40 ti,mux-clock} y @d!j!sys_ck@1270ti,divider-clock}!ypd&j&sys_clkout1@d70ti,gate-clock}!y pdpll3_x2_ckfixed-factor-clock}"%dpll3_m2x2_ckfixed-factor-clock}#%d%j%dpll4_x2_ckfixed-factor-clock}$%corex2_fckfixed-factor-clock}%%d'j'wkup_l4_ickfixed-factor-clock}&%dVjVcorex2_d3_fckfixed-factor-clock}'%djcorex2_d5_fckfixed-factor-clock}'%djclockdomainscm@48004000 ti,omap3-cmyH@@clocks+dummy_apb_pclk fixed-clockomap_32k_fck fixed-clockdHjHvirt_12m_ck fixed-clockdjvirt_13m_ck fixed-clock]@djvirt_19200000_ck fixed-clock$djvirt_26000000_ck fixed-clockdjvirt_38_4m_ck fixed-clockIdjdpll4_ck@d00ti,omap3-dpll-per-clock}&&y D 0d$j$dpll4_m2_ck@d48ti,divider-clock}$?y Hd(j(dpll4_m2x2_mul_ckfixed-factor-clock}(%d)j)dpll4_m2x2_ck@d00ti,gate-clock})y /d*j*omap_96m_alwon_fckfixed-factor-clock}*%d1j1dpll3_ck@d00ti,omap3-dpll-core-clock}&&y @ 0d"j"dpll3_m3_ck@1140ti,divider-clock}"y@d+j+dpll3_m3x2_mul_ckfixed-factor-clock}+%d,j,dpll3_m3x2_ck@d00ti,gate-clock}, y /d-j-emu_core_alwon_ckfixed-factor-clock}-%djjjsys_altclk fixed-clockd6j6mcbsp_clks fixed-clockdjdpll3_m2_ck@d40ti,divider-clock}"y @d#j#core_ckfixed-factor-clock}#%d.j.dpll1_fck@940ti,divider-clock}.y @d/j/dpll1_ck@904ti,omap3-dpll-clock}&/y  $ @ 4djdpll1_x2_ckfixed-factor-clock}%d0j0dpll1_x2m2_ck@944ti,divider-clock}0y DdDjDcm_96m_fckfixed-factor-clock}1%d2j2omap_96m_fck@d40 ti,mux-clock}2&y @dMjMdpll4_m3_ck@e40ti,divider-clock}$ y@d3j3dpll4_m3x2_mul_ckfixed-factor-clock}3%d4j4dpll4_m3x2_ck@d00ti,gate-clock}4y /d5j5omap_54m_fck@d40 ti,mux-clock}56y @d@j@cm_96m_d2_fckfixed-factor-clock}2%d7j7omap_48m_fck@d40 ti,mux-clock}76y @d8j8omap_12m_fckfixed-factor-clock}8%dOjOdpll4_m4_ck@e40ti,divider-clock}$ y@d9j9dpll4_m4x2_mul_ckti,fixed-factor-clock}9ES`d:j:dpll4_m4x2_ck@d00ti,gate-clock}:y /`djdpll4_m5_ck@f40ti,divider-clock}$?y@d;j;dpll4_m5x2_mul_ckti,fixed-factor-clock};ES`d<j<dpll4_m5x2_ck@d00ti,gate-clock}<y /`drjrdpll4_m6_ck@1140ti,divider-clock}$?y@d=j=dpll4_m6x2_mul_ckfixed-factor-clock}=%d>j>dpll4_m6x2_ck@d00ti,gate-clock}>y /d?j?emu_per_alwon_ckfixed-factor-clock}?%dkjkclkout2_src_gate_ck@d70 ti,composite-no-wait-gate-clock}.y pdAjAclkout2_src_mux_ck@d70ti,composite-mux-clock}.&2@y pdBjBclkout2_src_ckti,composite-clock}ABdCjCsys_clkout2@d70ti,divider-clock}C@y psmpu_ckfixed-factor-clock}D%dEjEarm_fck@924ti,divider-clock}Ey $emu_mpu_alwon_ckfixed-factor-clock}E%dljll3_ick@a40ti,divider-clock}.y @dFjFl4_ick@a40ti,divider-clock}Fy @dGjGrm_ick@c40ti,divider-clock}Gy @gpt10_gate_fck@a00ti,composite-gate-clock}& y dIjIgpt10_mux_fck@a40ti,composite-mux-clock}H&y @dJjJgpt10_fckti,composite-clock}IJgpt11_gate_fck@a00ti,composite-gate-clock}& y dKjKgpt11_mux_fck@a40ti,composite-mux-clock}H&y @dLjLgpt11_fckti,composite-clock}KLcore_96m_fckfixed-factor-clock}M%d j mmchs2_fck@a00ti,wait-gate-clock} y djmmchs1_fck@a00ti,wait-gate-clock} y dji2c3_fck@a00ti,wait-gate-clock} y dji2c2_fck@a00ti,wait-gate-clock} y dji2c1_fck@a00ti,wait-gate-clock} y djmcbsp5_gate_fck@a00ti,composite-gate-clock} y djmcbsp1_gate_fck@a00ti,composite-gate-clock} y djcore_48m_fckfixed-factor-clock}8%dNjNmcspi4_fck@a00ti,wait-gate-clock}Ny djmcspi3_fck@a00ti,wait-gate-clock}Ny djmcspi2_fck@a00ti,wait-gate-clock}Ny djmcspi1_fck@a00ti,wait-gate-clock}Ny djuart2_fck@a00ti,wait-gate-clock}Ny djuart1_fck@a00ti,wait-gate-clock}Ny  djcore_12m_fckfixed-factor-clock}O%dPjPhdq_fck@a00ti,wait-gate-clock}Py djcore_l3_ickfixed-factor-clock}F%dQjQsdrc_ick@a10ti,wait-gate-clock}Qy djgpmc_fckfixed-factor-clock}Q%core_l4_ickfixed-factor-clock}G%dRjRmmchs2_ick@a10ti,omap3-interface-clock}Ry djmmchs1_ick@a10ti,omap3-interface-clock}Ry djhdq_ick@a10ti,omap3-interface-clock}Ry djmcspi4_ick@a10ti,omap3-interface-clock}Ry djmcspi3_ick@a10ti,omap3-interface-clock}Ry djmcspi2_ick@a10ti,omap3-interface-clock}Ry djmcspi1_ick@a10ti,omap3-interface-clock}Ry dji2c3_ick@a10ti,omap3-interface-clock}Ry dji2c2_ick@a10ti,omap3-interface-clock}Ry dji2c1_ick@a10ti,omap3-interface-clock}Ry djuart2_ick@a10ti,omap3-interface-clock}Ry djuart1_ick@a10ti,omap3-interface-clock}Ry  djgpt11_ick@a10ti,omap3-interface-clock}Ry  djgpt10_ick@a10ti,omap3-interface-clock}Ry  djmcbsp5_ick@a10ti,omap3-interface-clock}Ry  djmcbsp1_ick@a10ti,omap3-interface-clock}Ry  djomapctrl_ick@a10ti,omap3-interface-clock}Ry djdss_tv_fck@e00ti,gate-clock}@ydjdss_96m_fck@e00ti,gate-clock}Mydjdss2_alwon_fck@e00ti,gate-clock}&ydjdummy_ck fixed-clockgpt1_gate_fck@c00ti,composite-gate-clock}&y dSjSgpt1_mux_fck@c40ti,composite-mux-clock}H&y @dTjTgpt1_fckti,composite-clock}STaes2_ick@a10ti,omap3-interface-clock}Ry djwkup_32k_fckfixed-factor-clock}H%dUjUgpio1_dbck@c00ti,gate-clock}Uy djsha12_ick@a10ti,omap3-interface-clock}Ry djwdt2_fck@c00ti,wait-gate-clock}Uy djwdt2_ick@c10ti,omap3-interface-clock}Vy djwdt1_ick@c10ti,omap3-interface-clock}Vy djgpio1_ick@c10ti,omap3-interface-clock}Vy djomap_32ksync_ick@c10ti,omap3-interface-clock}Vy djgpt12_ick@c10ti,omap3-interface-clock}Vy djgpt1_ick@c10ti,omap3-interface-clock}Vy djper_96m_fckfixed-factor-clock}1%djper_48m_fckfixed-factor-clock}8%dWjWuart3_fck@1000ti,wait-gate-clock}Wy djgpt2_gate_fck@1000ti,composite-gate-clock}&ydXjXgpt2_mux_fck@1040ti,composite-mux-clock}H&y@dYjYgpt2_fckti,composite-clock}XYgpt3_gate_fck@1000ti,composite-gate-clock}&ydZjZgpt3_mux_fck@1040ti,composite-mux-clock}H&y@d[j[gpt3_fckti,composite-clock}Z[gpt4_gate_fck@1000ti,composite-gate-clock}&yd\j\gpt4_mux_fck@1040ti,composite-mux-clock}H&y@d]j]gpt4_fckti,composite-clock}\]gpt5_gate_fck@1000ti,composite-gate-clock}&yd^j^gpt5_mux_fck@1040ti,composite-mux-clock}H&y@d_j_gpt5_fckti,composite-clock}^_gpt6_gate_fck@1000ti,composite-gate-clock}&yd`j`gpt6_mux_fck@1040ti,composite-mux-clock}H&y@dajagpt6_fckti,composite-clock}`agpt7_gate_fck@1000ti,composite-gate-clock}&ydbjbgpt7_mux_fck@1040ti,composite-mux-clock}H&y@dcjcgpt7_fckti,composite-clock}bcgpt8_gate_fck@1000ti,composite-gate-clock}& yddjdgpt8_mux_fck@1040ti,composite-mux-clock}H&y@dejegpt8_fckti,composite-clock}degpt9_gate_fck@1000ti,composite-gate-clock}& ydfjfgpt9_mux_fck@1040ti,composite-mux-clock}H&y@dgjggpt9_fckti,composite-clock}fgper_32k_alwon_fckfixed-factor-clock}H%dhjhgpio6_dbck@1000ti,gate-clock}hydjgpio5_dbck@1000ti,gate-clock}hydjgpio4_dbck@1000ti,gate-clock}hydjgpio3_dbck@1000ti,gate-clock}hydjgpio2_dbck@1000ti,gate-clock}hy djwdt3_fck@1000ti,wait-gate-clock}hy djper_l4_ickfixed-factor-clock}G%dijigpio6_ick@1010ti,omap3-interface-clock}iydjgpio5_ick@1010ti,omap3-interface-clock}iydjgpio4_ick@1010ti,omap3-interface-clock}iydjgpio3_ick@1010ti,omap3-interface-clock}iydjgpio2_ick@1010ti,omap3-interface-clock}iy djwdt3_ick@1010ti,omap3-interface-clock}iy djuart3_ick@1010ti,omap3-interface-clock}iy djuart4_ick@1010ti,omap3-interface-clock}iydjgpt9_ick@1010ti,omap3-interface-clock}iy djgpt8_ick@1010ti,omap3-interface-clock}iy djgpt7_ick@1010ti,omap3-interface-clock}iydjgpt6_ick@1010ti,omap3-interface-clock}iydjgpt5_ick@1010ti,omap3-interface-clock}iydjgpt4_ick@1010ti,omap3-interface-clock}iydjgpt3_ick@1010ti,omap3-interface-clock}iydjgpt2_ick@1010ti,omap3-interface-clock}iydjmcbsp2_ick@1010ti,omap3-interface-clock}iydjmcbsp3_ick@1010ti,omap3-interface-clock}iydjmcbsp4_ick@1010ti,omap3-interface-clock}iydjmcbsp2_gate_fck@1000ti,composite-gate-clock}ydjmcbsp3_gate_fck@1000ti,composite-gate-clock}ydjmcbsp4_gate_fck@1000ti,composite-gate-clock}ydjemu_src_mux_ck@1140 ti,mux-clock}&jkly@dmjmemu_src_ckti,clkdm-gate-clock}mdnjnpclk_fck@1140ti,divider-clock}ny@pclkx2_fck@1140ti,divider-clock}ny@atclk_fck@1140ti,divider-clock}ny@traceclk_src_fck@1140 ti,mux-clock}&jkly@dojotraceclk_fck@1140ti,divider-clock}o y@secure_32k_fck fixed-clockdpjpgpt12_fckfixed-factor-clock}p%wdt1_fckfixed-factor-clock}p%security_l4_ick2fixed-factor-clock}G%dqjqaes1_ick@a14ti,omap3-interface-clock}qy rng_ick@a14ti,omap3-interface-clock}qy sha11_ick@a14ti,omap3-interface-clock}qy des1_ick@a14ti,omap3-interface-clock}qy cam_mclk@f00ti,gate-clock}ry`cam_ick@f10!ti,omap3-no-wait-interface-clock}Gydjcsi2_96m_fck@f00ti,gate-clock} ydjsecurity_l3_ickfixed-factor-clock}F%dsjspka_ick@a14ti,omap3-interface-clock}sy icr_ick@a10ti,omap3-interface-clock}Ry des2_ick@a10ti,omap3-interface-clock}Ry mspro_ick@a10ti,omap3-interface-clock}Ry mailboxes_ick@a10ti,omap3-interface-clock}Ry ssi_l4_ickfixed-factor-clock}G%dzjzsr1_fck@c00ti,wait-gate-clock}&y sr2_fck@c00ti,wait-gate-clock}&y sr_l4_ickfixed-factor-clock}G%dpll2_fck@40ti,divider-clock}.y@dtjtdpll2_ck@4ti,omap3-dpll-clock}&ty$@4dujudpll2_m2_ck@44ti,divider-clock}uyDdvjviva2_ck@0ti,wait-gate-clock}vydjmodem_fck@a00ti,omap3-interface-clock}&y djsad2d_ick@a10ti,omap3-interface-clock}Fy djmad2d_ick@a18ti,omap3-interface-clock}Fy djmspro_fck@a00ti,wait-gate-clock} y ssi_ssr_gate_fck_3430es2@a00 ti,composite-no-wait-gate-clock}'y dwjwssi_ssr_div_fck_3430es2@a40ti,composite-divider-clock}'y @$dxjxssi_ssr_fck_3430es2ti,composite-clock}wxdyjyssi_sst_fck_3430es2fixed-factor-clock}y%djhsotgusb_ick_3430es2@a10"ti,omap3-hsotgusb-interface-clock}Qy djssi_ick_3430es2@a10ti,omap3-ssi-interface-clock}zy djusim_gate_fck@c00ti,composite-gate-clock}M y djsys_d2_ckfixed-factor-clock}&%d|j|omap_96m_d2_fckfixed-factor-clock}M%d}j}omap_96m_d4_fckfixed-factor-clock}M%d~j~omap_96m_d8_fckfixed-factor-clock}M%djomap_96m_d10_fckfixed-factor-clock}M% djdpll5_m2_d4_ckfixed-factor-clock}{%djdpll5_m2_d8_ckfixed-factor-clock}{%djdpll5_m2_d16_ckfixed-factor-clock}{%djdpll5_m2_d20_ckfixed-factor-clock}{%djusim_mux_fck@c40ti,composite-mux-clock(}&|}~y @djusim_fckti,composite-clock}usim_ick@c10ti,omap3-interface-clock}Vy  djdpll5_ck@d04ti,omap3-dpll-clock}&&y  $ L 4djdpll5_m2_ck@d50ti,divider-clock}y Pd{j{sgx_gate_fck@b00ti,composite-gate-clock}.y djcore_d3_ckfixed-factor-clock}.%djcore_d4_ckfixed-factor-clock}.%djcore_d6_ckfixed-factor-clock}.%djomap_192m_alwon_fckfixed-factor-clock}*%djcore_d2_ckfixed-factor-clock}.%djsgx_mux_fck@b40ti,composite-mux-clock }2y @djsgx_fckti,composite-clock}sgx_ick@b10ti,wait-gate-clock}Fy djcpefuse_fck@a08ti,gate-clock}&y djts_fck@a08ti,gate-clock}Hy djusbtll_fck@a08ti,wait-gate-clock}{y djusbtll_ick@a18ti,omap3-interface-clock}Ry djmmchs3_ick@a10ti,omap3-interface-clock}Ry djmmchs3_fck@a00ti,wait-gate-clock} y djdss1_alwon_fck_3430es2@e00ti,dss-gate-clock}y`djdss_ick_3430es2@e10ti,omap3-dss-interface-clock}Gydjusbhost_120m_fck@1400ti,gate-clock}{ydjusbhost_48m_fck@1400ti,dss-gate-clock}8ydjusbhost_ick@1410ti,omap3-dss-interface-clock}Gydjclockdomainscore_l3_clkdmti,clockdomain}dpll3_clkdmti,clockdomain}"dpll1_clkdmti,clockdomain}per_clkdmti,clockdomainh}emu_clkdmti,clockdomain}ndpll4_clkdmti,clockdomain}$wkup_clkdmti,clockdomain$}dss_clkdmti,clockdomain}core_l4_clkdmti,clockdomain}cam_clkdmti,clockdomain}iva2_clkdmti,clockdomain}dpll2_clkdmti,clockdomain}ud2d_clkdmti,clockdomain }dpll5_clkdmti,clockdomain}sgx_clkdmti,clockdomain}usbhost_clkdmti,clockdomain }counter@48320000ti,omap-counter32kyH2  counter_32kinterrupt-controller@48200000ti,omap3-intcyH djdma-controller@48056000"ti,omap3630-sdmati,omap3430-sdmayH`  `djgpio@48310000ti,omap3-gpioyH1gpio1 gpio@49050000ti,omap3-gpioyIgpio2 gpio@49052000ti,omap3-gpioyI gpio3 gpio@49054000ti,omap3-gpioyI@ gpio4 gpio@49056000ti,omap3-gpioyI`!gpio5 d j gpio@49058000ti,omap3-gpioyI"gpio6 d j serial@4806a000ti,omap3-uartyH H12txrxuart1lserial@4806c000ti,omap3-uartyHI34txrxuart2lserial@49020000ti,omap3-uartyIJ56txrxuart3l8defaultFi2c@48070000 ti,omap3-i2cyH8txrx+i2c1'@twl@48yH  ti,twl40308defaultFaudioti,twl4030-audiocodecrtcti,twl4030-rtc bciti,twl4030-bci *watchdogti,twl4030-wdtregulator-vaux1ti,twl4030-vaux1regulator-vaux2ti,twl4030-vaux2 yvdd_ehciw@w@8regulator-vaux3ti,twl4030-vaux3regulator-vaux4ti,twl4030-vaux4regulator-vdd1ti,twl4030-vdd1 ' djregulator-vdacti,twl4030-vdacw@w@regulator-vioti,twl4030-vioregulator-vintana1ti,twl4030-vintana1regulator-vintana2ti,twl4030-vintana2regulator-vintdigti,twl4030-vintdigregulator-vmmc1ti,twl4030-vmmc1:0djregulator-vmmc2ti,twl4030-vmmc2:0regulator-vusb1v5ti,twl4030-vusb1v5djregulator-vusb1v8ti,twl4030-vusb1v8djregulator-vusb3v1ti,twl4030-vusb3v1djregulator-vpll1ti,twl4030-vpll1regulator-vpll2ti,twl4030-vpll2w@w@8regulator-vsimti,twl4030-vsimw@-djgpioti,twl4030-gpio LXcdjtwl4030-usbti,twl4030-usb p~djpwmti,twl4030-pwmpwmledti,twl4030-pwmledpwrbuttonti,twl4030-pwrbuttonkeypadti,twl4030-keypadmadcti,twl4030-madci2c@48072000 ti,omap3-i2cyH 9txrx+i2c2 disabledi2c@48060000 ti,omap3-i2cyH=txrx+i2c38defaultFmailbox@48094000ti,omap3-mailboxmailboxyH @ dsp  )spi@48098000ti,omap2-mcspiyH A+mcspi14@#$%&'()* tx0rx0tx1rx1tx2rx2tx3rx38defaultFspidev@0spidevBlyTspi@4809a000ti,omap2-mcspiyH B+mcspi24 +,-.tx0rx0tx1rx1spi@480b8000ti,omap2-mcspiyH [+mcspi34 tx0rx0tx1rx18defaultFspidev@0spidevBlyTspi@480ba000ti,omap2-mcspiyH 0+mcspi44FGtx0rx01w@480b2000 ti,omap3-1wyH :hdq1wmmc@4809c000ti,omap3-hsmmcyH Smmc1]=>txrxj8defaultFw mmc@480b4000ti,omap3-hsmmcyH @Vmmc2/0txrx8defaultFwmmc@480ad000ti,omap3-hsmmcyH ^mmc3MNtxrx disabledmmu@480bd400ti,omap2-iommuyH mmu_ispdjmmu@5d000000ti,omap2-iommuy]mmu_iva disabledwdt@48314000 ti,omap3-wdtyH1@ wd_timer2mcbsp@48074000ti,omap3-mcbspyH@mpu ;< commontxrxmcbsp1 txrx}fck disabledmcbsp@49022000ti,omap3-mcbspyI I mpusidetone>?commontxrxsidetonemcbsp2mcbsp2_sidetone!"txrx}fckickokayd j mcbsp@49024000ti,omap3-mcbspyI@I mpusidetoneYZcommontxrxsidetonemcbsp3mcbsp3_sidetonetxrx}fckickokay8defaultFmcbsp@49026000ti,omap3-mcbspyI`mpu 67 commontxrxmcbsp4txrx}fck disabledmcbsp@48096000ti,omap3-mcbspyH `mpu QR commontxrxmcbsp5txrx}fck disabledsham@480c3000ti,omap3-shamshamyH 0d1Erx disabledsmartreflex@480cb000ti,omap3-smartreflex-coresmartreflex_coreyH smartreflex@480c9000ti,omap3-smartreflex-ivasmartreflex_mpu_ivayH timer@48318000ti,omap3430-timeryH1%timer1 timer@49032000ti,omap3430-timeryI &timer2timer@49034000ti,omap3430-timeryI@'timer3timer@49036000ti,omap3430-timeryI`(timer4timer@49038000ti,omap3430-timeryI)timer5timer@4903a000ti,omap3430-timeryI*timer6timer@4903c000ti,omap3430-timeryI+timer7timer@4903e000ti,omap3430-timeryI,timer8)timer@49040000ti,omap3430-timeryI-timer9)timer@48086000ti,omap3430-timeryH`.timer10)timer@48088000ti,omap3430-timeryH/timer11)timer@48304000ti,omap3430-timeryH0@_timer12 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ti,omap3-ispyH H |r lports+bandgap@48002524yH%$ti,omap34xx-bandgapmemory@80000000mmemoryyhsusb2_power_regregulator-fixed yhsusb2_vbus2Z2Z pd j hsusb2_phyusb-nop-xceiv , 8 djsoundti,omap-twl4030 Comap3beagleL regulator-mmc2-sdio-poweronregulator-fixedyregulator-mmc2-sdio-poweron00  U'djgpio_poweroff8defaultF gpio-poweroff  display panel-dpilcd8defaultF g portendpointdjpanel-timingPt |(V backlightgpio-backlight8defaultF   compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2serial0serial1serial2display0device_typeregclocksclock-namesclock-latencyoperating-pointscpu0-supplyinterruptsti,hwmodsranges#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0pinctrl-single,pinslinux,phandlesysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftdmasdma-namesstatusclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividers#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedbci3v1-supplyregulator-always-onti,use-ledsti,pullupsti,pulldownsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columns#io-channel-cells#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csspi-max-frequencyspi-cphati,dual-voltpbias-supplyvmmc-supplyvmmc_aux-supplycd-gpiosbus-widthnon-removablecap-power-off-card#iommu-cellsti,#tlb-entriesreg-namesinterrupt-namesti,buffer-sizeti,timer-alwonti,timer-dspti,timer-pwmti,timer-secureport2-modephysgpmc,num-csgpmc,num-waitpinsnand-bus-widthgpmc,device-widthti,nand-ecc-optgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,oe-on-nsgpmc,oe-off-nsgpmc,we-on-nsgpmc,we-off-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,access-nsgpmc,wr-access-nslabelmultipointnum-epsram-bitsinterface-typeusb-phyphy-namespowerremote-endpointdata-linesiommusti,phy-type#thermal-sensor-cellsgpiostartup-delay-usreset-gpiosvcc-supplyti,modelti,mcbspenable-active-lowenable-gpioshactivevactivehfront-porchhback-porchhsync-lenvback-porchvfront-porchvsync-lenhsync-activevsync-activede-activepixelclk-activedefault-on