8(9؜teejet,mt_ventouxti,omap3 +7TeeJet Mt.Ventouxchosenaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/serial@4806a000T/ocp@68000000/serial@4806c000\/ocp@68000000/serial@49020000cpus+cpu@0arm,cortex-a8dcpupt{cpu(HАg8 Odp` 'ppmu@54000000arm,cortex-a8-pmupTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2iva disableddsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-busph +l3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-busp + pinmux@30 ti,omap3-padconfpinctrl-singlep08+ scm_conf@270sysconsimple-buspp0+ p0*0pbias_regulator@2b0ti,pbias-omap3ti,pbias-omapp8pbias_mmc_omap2430?pbias_mmc_omap2430Nw@f-*0clocks+mcbsp5_mux_fck@68~ti,composite-mux-clocktph*0mcbsp5_fck~ti,composite-clockt*0mcbsp1_mux_fck@4~ti,composite-mux-clocktp* 0 mcbsp1_fck~ti,composite-clockt *0mcbsp2_mux_fck@4~ti,composite-mux-clockt p* 0 mcbsp2_fck~ti,composite-clockt *0mcbsp3_mux_fck@68~ti,composite-mux-clockt ph*0mcbsp3_fck~ti,composite-clockt *0mcbsp4_mux_fck@68~ti,composite-mux-clockt ph*0mcbsp4_fck~ti,composite-clockt*0clockdomainspinmux@a00 ti,omap3-padconfpinctrl-singlep \+ aes@480c5000 ti,omap3-aesaespH PPABtxrxprm@48306000 ti,omap3-prmpH0`@ clocks+virt_16_8m_ck~ fixed-clockY*0osc_sys_ck@d40~ ti,mux-clocktp @*0sys_ck@1270~ti,divider-clocktpp*0sys_clkout1@d70~ti,gate-clocktp pdpll3_x2_ck~fixed-factor-clocktdpll3_m2x2_ck~fixed-factor-clockt*0dpll4_x2_ck~fixed-factor-clocktcorex2_fck~fixed-factor-clockt*0wkup_l4_ick~fixed-factor-clockt*M0Mcorex2_d3_fck~fixed-factor-clockt*0corex2_d5_fck~fixed-factor-clockt*0clockdomainscm@48004000 ti,omap3-cmpH@@clocks+dummy_apb_pclk~ fixed-clockomap_32k_fck~ fixed-clock*?0?virt_12m_ck~ fixed-clock*0virt_13m_ck~ fixed-clock]@*0virt_19200000_ck~ fixed-clock$*0virt_26000000_ck~ fixed-clock*0virt_38_4m_ck~ fixed-clockI*0dpll4_ck@d00~ti,omap3-dpll-per-clocktp D 0*0dpll4_m2_ck@d48~ti,divider-clockt?p H*0dpll4_m2x2_mul_ck~fixed-factor-clockt* 0 dpll4_m2x2_ck@d00~ti,gate-clockt p *!0!omap_96m_alwon_fck~fixed-factor-clockt!*(0(dpll3_ck@d00~ti,omap3-dpll-core-clocktp @ 0*0dpll3_m3_ck@1140~ti,divider-clocktp@*"0"dpll3_m3x2_mul_ck~fixed-factor-clockt"*#0#dpll3_m3x2_ck@d00~ti,gate-clockt# p *$0$emu_core_alwon_ck~fixed-factor-clockt$*a0asys_altclk~ fixed-clock*-0-mcbsp_clks~ fixed-clock*0dpll3_m2_ck@d40~ti,divider-clocktp @*0core_ck~fixed-factor-clockt*%0%dpll1_fck@940~ti,divider-clockt%p @*&0&dpll1_ck@904~ti,omap3-dpll-clockt&p  $ @ 4*0dpll1_x2_ck~fixed-factor-clockt*'0'dpll1_x2m2_ck@944~ti,divider-clockt'p D*;0;cm_96m_fck~fixed-factor-clockt(*)0)omap_96m_fck@d40~ ti,mux-clockt)p @*D0Ddpll4_m3_ck@e40~ti,divider-clockt p@**0*dpll4_m3x2_mul_ck~fixed-factor-clockt**+0+dpll4_m3x2_ck@d00~ti,gate-clockt+p *,0,omap_54m_fck@d40~ ti,mux-clockt,-p @*707cm_96m_d2_fck~fixed-factor-clockt)*.0.omap_48m_fck@d40~ ti,mux-clockt.-p @*/0/omap_12m_fck~fixed-factor-clockt/*F0Fdpll4_m4_ck@e40~ti,divider-clockt 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*B0Bgpt11_mux_fck@a40~ti,composite-mux-clockt?p @*C0Cgpt11_fck~ti,composite-clocktBCcore_96m_fck~fixed-factor-clocktD*0mmchs2_fck@a00~ti,wait-gate-clocktp *0mmchs1_fck@a00~ti,wait-gate-clocktp *0i2c3_fck@a00~ti,wait-gate-clocktp *0i2c2_fck@a00~ti,wait-gate-clocktp *0i2c1_fck@a00~ti,wait-gate-clocktp *0mcbsp5_gate_fck@a00~ti,composite-gate-clockt p *0mcbsp1_gate_fck@a00~ti,composite-gate-clockt p *0core_48m_fck~fixed-factor-clockt/*E0Emcspi4_fck@a00~ti,wait-gate-clocktEp *0mcspi3_fck@a00~ti,wait-gate-clocktEp *0mcspi2_fck@a00~ti,wait-gate-clocktEp *0mcspi1_fck@a00~ti,wait-gate-clocktEp *0uart2_fck@a00~ti,wait-gate-clocktEp *0uart1_fck@a00~ti,wait-gate-clocktEp  *0core_12m_fck~fixed-factor-clocktF*G0Ghdq_fck@a00~ti,wait-gate-clocktGp *0core_l3_ick~fixed-factor-clockt=*H0Hsdrc_ick@a10~ti,wait-gate-clocktHp *0gpmc_fck~fixed-factor-clocktHcore_l4_ick~fixed-factor-clockt>*I0Immchs2_ick@a10~ti,omap3-interface-clocktIp *0mmchs1_ick@a10~ti,omap3-interface-clocktIp *0hdq_ick@a10~ti,omap3-interface-clocktIp *0mcspi4_ick@a10~ti,omap3-interface-clocktIp *0mcspi3_ick@a10~ti,omap3-interface-clocktIp *0mcspi2_ick@a10~ti,omap3-interface-clocktIp *0mcspi1_ick@a10~ti,omap3-interface-clocktIp *0i2c3_ick@a10~ti,omap3-interface-clocktIp *0i2c2_ick@a10~ti,omap3-interface-clocktIp *0i2c1_ick@a10~ti,omap3-interface-clocktIp *0uart2_ick@a10~ti,omap3-interface-clocktIp *0uart1_ick@a10~ti,omap3-interface-clocktIp  *0gpt11_ick@a10~ti,omap3-interface-clocktIp  *0gpt10_ick@a10~ti,omap3-interface-clocktIp  *0mcbsp5_ick@a10~ti,omap3-interface-clocktIp  *0mcbsp1_ick@a10~ti,omap3-interface-clocktIp  *0omapctrl_ick@a10~ti,omap3-interface-clocktIp *0dss_tv_fck@e00~ti,gate-clockt7p*0dss_96m_fck@e00~ti,gate-clocktDp*0dss2_alwon_fck@e00~ti,gate-clocktp*0dummy_ck~ fixed-clockgpt1_gate_fck@c00~ti,composite-gate-clocktp *J0Jgpt1_mux_fck@c40~ti,composite-mux-clockt?p @*K0Kgpt1_fck~ti,composite-clocktJKaes2_ick@a10~ti,omap3-interface-clocktIp *0wkup_32k_fck~fixed-factor-clockt?*L0Lgpio1_dbck@c00~ti,gate-clocktLp *0sha12_ick@a10~ti,omap3-interface-clocktIp *0wdt2_fck@c00~ti,wait-gate-clocktLp *0wdt2_ick@c10~ti,omap3-interface-clocktMp *0wdt1_ick@c10~ti,omap3-interface-clocktMp *0gpio1_ick@c10~ti,omap3-interface-clocktMp *0omap_32ksync_ick@c10~ti,omap3-interface-clocktMp *0gpt12_ick@c10~ti,omap3-interface-clocktMp *0gpt1_ick@c10~ti,omap3-interface-clocktMp *0per_96m_fck~fixed-factor-clockt(* 0 per_48m_fck~fixed-factor-clockt/*N0Nuart3_fck@1000~ti,wait-gate-clocktNp *0gpt2_gate_fck@1000~ti,composite-gate-clocktp*O0Ogpt2_mux_fck@1040~ti,composite-mux-clockt?p@*P0Pgpt2_fck~ti,composite-clocktOPgpt3_gate_fck@1000~ti,composite-gate-clocktp*Q0Qgpt3_mux_fck@1040~ti,composite-mux-clockt?p@*R0Rgpt3_fck~ti,composite-clocktQRgpt4_gate_fck@1000~ti,composite-gate-clocktp*S0Sgpt4_mux_fck@1040~ti,composite-mux-clockt?p@*T0Tgpt4_fck~ti,composite-clocktSTgpt5_gate_fck@1000~ti,composite-gate-clocktp*U0Ugpt5_mux_fck@1040~ti,composite-mux-clockt?p@*V0Vgpt5_fck~ti,composite-clocktUVgpt6_gate_fck@1000~ti,composite-gate-clocktp*W0Wgpt6_mux_fck@1040~ti,composite-mux-clockt?p@*X0Xgpt6_fck~ti,composite-clocktWXgpt7_gate_fck@1000~ti,composite-gate-clocktp*Y0Ygpt7_mux_fck@1040~ti,composite-mux-clockt?p@*Z0Zgpt7_fck~ti,composite-clocktYZgpt8_gate_fck@1000~ti,composite-gate-clockt p*[0[gpt8_mux_fck@1040~ti,composite-mux-clockt?p@*\0\gpt8_fck~ti,composite-clockt[\gpt9_gate_fck@1000~ti,composite-gate-clockt p*]0]gpt9_mux_fck@1040~ti,composite-mux-clockt?p@*^0^gpt9_fck~ti,composite-clockt]^per_32k_alwon_fck~fixed-factor-clockt?*_0_gpio6_dbck@1000~ti,gate-clockt_p*0gpio5_dbck@1000~ti,gate-clockt_p*0gpio4_dbck@1000~ti,gate-clockt_p*0gpio3_dbck@1000~ti,gate-clockt_p*0gpio2_dbck@1000~ti,gate-clockt_p *0wdt3_fck@1000~ti,wait-gate-clockt_p *0per_l4_ick~fixed-factor-clockt>*`0`gpio6_ick@1010~ti,omap3-interface-clockt`p*0gpio5_ick@1010~ti,omap3-interface-clockt`p*0gpio4_ick@1010~ti,omap3-interface-clockt`p*0gpio3_ick@1010~ti,omap3-interface-clockt`p*0gpio2_ick@1010~ti,omap3-interface-clockt`p *0wdt3_ick@1010~ti,omap3-interface-clockt`p *0uart3_ick@1010~ti,omap3-interface-clockt`p *0uart4_ick@1010~ti,omap3-interface-clockt`p*0gpt9_ick@1010~ti,omap3-interface-clockt`p *0gpt8_ick@1010~ti,omap3-interface-clockt`p *0gpt7_ick@1010~ti,omap3-interface-clockt`p*0gpt6_ick@1010~ti,omap3-interface-clockt`p*0gpt5_ick@1010~ti,omap3-interface-clockt`p*0gpt4_ick@1010~ti,omap3-interface-clockt`p*0gpt3_ick@1010~ti,omap3-interface-clockt`p*0gpt2_ick@1010~ti,omap3-interface-clockt`p*0mcbsp2_ick@1010~ti,omap3-interface-clockt`p*0mcbsp3_ick@1010~ti,omap3-interface-clockt`p*0mcbsp4_ick@1010~ti,omap3-interface-clockt`p*0mcbsp2_gate_fck@1000~ti,composite-gate-clocktp* 0 mcbsp3_gate_fck@1000~ti,composite-gate-clocktp* 0 mcbsp4_gate_fck@1000~ti,composite-gate-clocktp*0emu_src_mux_ck@1140~ ti,mux-clocktabcp@*d0demu_src_ck~ti,clkdm-gate-clocktd*e0epclk_fck@1140~ti,divider-clocktep@pclkx2_fck@1140~ti,divider-clocktep@atclk_fck@1140~ti,divider-clocktep@traceclk_src_fck@1140~ ti,mux-clocktabcp@*f0ftraceclk_fck@1140~ti,divider-clocktf p@secure_32k_fck~ fixed-clock*g0ggpt12_fck~fixed-factor-clocktgwdt1_fck~fixed-factor-clocktgsecurity_l4_ick2~fixed-factor-clockt>*h0haes1_ick@a14~ti,omap3-interface-clockthp rng_ick@a14~ti,omap3-interface-clockthp sha11_ick@a14~ti,omap3-interface-clockthp des1_ick@a14~ti,omap3-interface-clockthp cam_mclk@f00~ti,gate-clocktipcam_ick@f10~!ti,omap3-no-wait-interface-clockt>p*0csi2_96m_fck@f00~ti,gate-clocktp*0security_l3_ick~fixed-factor-clockt=*j0jpka_ick@a14~ti,omap3-interface-clocktjp icr_ick@a10~ti,omap3-interface-clocktIp des2_ick@a10~ti,omap3-interface-clocktIp mspro_ick@a10~ti,omap3-interface-clocktIp mailboxes_ick@a10~ti,omap3-interface-clocktIp ssi_l4_ick~fixed-factor-clockt>*q0qsr1_fck@c00~ti,wait-gate-clocktp sr2_fck@c00~ti,wait-gate-clocktp sr_l4_ick~fixed-factor-clockt>dpll2_fck@40~ti,divider-clockt%p@*k0kdpll2_ck@4~ti,omap3-dpll-clocktkp$@4HZb*l0ldpll2_m2_ck@44~ti,divider-clocktlpD*m0miva2_ck@0~ti,wait-gate-clocktmp*0modem_fck@a00~ti,omap3-interface-clocktp *0sad2d_ick@a10~ti,omap3-interface-clockt=p *0mad2d_ick@a18~ti,omap3-interface-clockt=p *0mspro_fck@a00~ti,wait-gate-clocktp ssi_ssr_gate_fck_3430es2@a00~ ti,composite-no-wait-gate-clocktp *n0nssi_ssr_div_fck_3430es2@a40~ti,composite-divider-clocktp @$v*o0ossi_ssr_fck_3430es2~ti,composite-clocktno*p0pssi_sst_fck_3430es2~fixed-factor-clocktp*0hsotgusb_ick_3430es2@a10~"ti,omap3-hsotgusb-interface-clocktHp *0ssi_ick_3430es2@a10~ti,omap3-ssi-interface-clocktqp *0usim_gate_fck@c00~ti,composite-gate-clocktD p *|0|sys_d2_ck~fixed-factor-clockt*s0somap_96m_d2_fck~fixed-factor-clocktD*t0tomap_96m_d4_fck~fixed-factor-clocktD*u0uomap_96m_d8_fck~fixed-factor-clocktD*v0vomap_96m_d10_fck~fixed-factor-clocktD *w0wdpll5_m2_d4_ck~fixed-factor-clocktr*x0xdpll5_m2_d8_ck~fixed-factor-clocktr*y0ydpll5_m2_d16_ck~fixed-factor-clocktr*z0zdpll5_m2_d20_ck~fixed-factor-clocktr*{0{usim_mux_fck@c40~ti,composite-mux-clock(tstuvwxyz{p @*}0}usim_fck~ti,composite-clockt|}usim_ick@c10~ti,omap3-interface-clocktMp  *0dpll5_ck@d04~ti,omap3-dpll-clocktp  $ L 4HZ*~0~dpll5_m2_ck@d50~ti,divider-clockt~p P*r0rsgx_gate_fck@b00~ti,composite-gate-clockt%p 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*0dss1_alwon_fck_3430es2@e00~ti,dss-gate-clocktp*0dss_ick_3430es2@e10~ti,omap3-dss-interface-clockt>p*0usbhost_120m_fck@1400~ti,gate-clocktrp*0usbhost_48m_fck@1400~ti,dss-gate-clockt/p*0usbhost_ick@1410~ti,omap3-dss-interface-clockt>p*0clockdomainscore_l3_clkdmti,clockdomaintdpll3_clkdmti,clockdomaintdpll1_clkdmti,clockdomaintper_clkdmti,clockdomainhtemu_clkdmti,clockdomaintedpll4_clkdmti,clockdomaintwkup_clkdmti,clockdomain$tdss_clkdmti,clockdomaintcore_l4_clkdmti,clockdomaintcam_clkdmti,clockdomaintiva2_clkdmti,clockdomaintdpll2_clkdmti,clockdomaintld2d_clkdmti,clockdomain tdpll5_clkdmti,clockdomaint~sgx_clkdmti,clockdomaintusbhost_clkdmti,clockdomain tcounter@48320000ti,omap-counter32kpH2  counter_32kinterrupt-controller@48200000ti,omap3-intcpH *0dma-controller@48056000"ti,omap3630-sdmati,omap3430-sdmapH`  `*0gpio@48310000ti,omap3-gpiopH1gpio1gpio@49050000ti,omap3-gpiopIgpio2gpio@49052000ti,omap3-gpiopI gpio3gpio@49054000ti,omap3-gpiopI@ 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&timer2timer@49034000ti,omap3430-timerpI@'timer3timer@49036000ti,omap3430-timerpI`(timer4timer@49038000ti,omap3430-timerpI)timer5timer@4903a000ti,omap3430-timerpI*timer6timer@4903c000ti,omap3430-timerpI+timer7timer@4903e000ti,omap3430-timerpI,timer8timer@49040000ti,omap3430-timerpI-timer9timer@48086000ti,omap3430-timerpH`.timer10timer@48088000ti,omap3430-timerpH/timer11timer@48304000ti,omap3430-timerpH0@_timer12usbhstll@48062000 ti,usbhs-tllpH N usb_tll_hsusbhshost@48064000ti,usbhs-hostpH@ usb_host_hs+ohci@48064400ti,ohci-omap3pHD Lehci@48064800 ti,ehci-omappHH Mgpmc@6e000000ti,omap3430-gpmcgpmcpnrxtx+usb_otg_hs@480ab000ti,omap3-musbpH \]~mcdma usb_otg_hs dss@48050000 ti,omap3-dsspH disabled dss_coret{fck+dispc@48050400ti,omap3-dispcpH dss_dispct{fckencoder@4804fc00 ti,omap3-dsipHH@H tprotophypll disabled dss_dsi1t {fcksys_clkencoder@48050800ti,omap3-rfbipH disabled dss_rfbit{fckickencoder@48050c00ti,omap3-vencpH  disabled dss_venct{fckssi-controller@48058000 ti,omap3-ssissiokpHHtsysgddG~gdd_mpu+ tp {ssi_ssr_fckssi_sst_fckssi_ickssi-port@4805a000ti,omap3-ssi-portpHHttxrx CDssi-port@4805b000ti,omap3-ssi-portpHHttxrx EFpinmux@480025d8 ti,omap3-padconfpinctrl-singlepH%$+ isp@480bc000 ti,omap3-isppH H |8l~ports+bandgap@48002524pH%$ti,omap34xx-bandgap#memory@80000000dmemoryp compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2serial0serial1serial2device_typeregclocksclock-namesclock-latencyoperating-pointsinterruptsti,hwmodsstatusranges#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-masklinux,phandlesysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividers#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extended#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csti,dual-voltpbias-supply#iommu-cellsti,#tlb-entriesreg-namesinterrupt-namesti,buffer-sizeti,timer-alwonti,timer-dspti,timer-pwmti,timer-securegpmc,num-csgpmc,num-waitpinsmultipointnum-epsram-bitsiommusti,phy-type#thermal-sensor-cells