8̀(rH(ti,am3517-craneboardti,am3517ti,omap3 +#7TI AM3517 CraneBoard (TMDSEVM3517)chosenaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/serial@4806a000T/ocp@68000000/serial@4806c000\/ocp@68000000/serial@49020000d/ocp@68000000/serial@4809e000cpus+cpu@0arm,cortex-a8lcpux|cpupmu@54000000arm,cortex-a8-pmuxTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2iva disableddsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-busxh +l3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-busx + pinmux@30 ti,omap3-padconfpinctrl-singlex08+pinmux_tps_pins!5;scm_conf@270sysconsimple-busxp0+ p05;pbias_regulator@2b0ti,pbias-omap3ti,pbias-omapxCpbias_mmc_omap2430Jpbias_mmc_omap2430Yw@q-5;clocks+mcbsp5_mux_fck@68ti,composite-mux-clock|xh5;mcbsp5_fckti,composite-clock|5;mcbsp1_mux_fck@4ti,composite-mux-clock|x5 ; mcbsp1_fckti,composite-clock| 5;mcbsp2_mux_fck@4ti,composite-mux-clock| x5 ; mcbsp2_fckti,composite-clock| 5;mcbsp3_mux_fck@68ti,composite-mux-clock| xh5;mcbsp3_fckti,composite-clock| 5;mcbsp4_mux_fck@68ti,composite-mux-clock| xh5;mcbsp4_fckti,composite-clock|5;emac_ick@32cti,am35xx-gate-clock|x,5x;xemac_fck@32cti,gate-clock|x, vpfe_ick@32cti,am35xx-gate-clock|x,5y;yvpfe_fck@32cti,gate-clock|x, hsotgusb_ick_am35xx@32cti,am35xx-gate-clock|x,5z;zhsotgusb_fck_am35xx@32cti,gate-clock|x,5{;{hecc_ck@32cti,am35xx-gate-clock|x,5|;|clockdomainspinmux@a00 ti,omap3-padconfpinctrl-singlex \+aes@480c5000 ti,omap3-aesaesxH PPABtxrxprm@48306000 ti,omap3-prmxH0`@ clocks+virt_16_8m_ck fixed-clockY5;osc_sys_ck@d40 ti,mux-clock|x @5;sys_ck@1270ti,divider-clock|xp5;sys_clkout1@d70ti,gate-clock|x pdpll3_x2_ckfixed-factor-clock|dpll3_m2x2_ckfixed-factor-clock|5 ; dpll4_x2_ckfixed-factor-clock|corex2_fckfixed-factor-clock| 5!;!wkup_l4_ickfixed-factor-clock|5P;Pcorex2_d3_fckfixed-factor-clock|!5q;qcorex2_d5_fckfixed-factor-clock|!5r;rclockdomainscm@48004000 ti,omap3-cmxH@@clocks+dummy_apb_pclk fixed-clockomap_32k_fck fixed-clock5B;Bvirt_12m_ck fixed-clock5;virt_13m_ck fixed-clock]@5;virt_19200000_ck fixed-clock$5;virt_26000000_ck fixed-clock5;virt_38_4m_ck fixed-clockI5;dpll4_ck@d00ti,omap3-dpll-per-clock|x D 05;dpll4_m2_ck@d48ti,divider-clock|?x H5";"dpll4_m2x2_mul_ckfixed-factor-clock|"5#;#dpll4_m2x2_ck@d00ti,gate-clock|#x 5$;$omap_96m_alwon_fckfixed-factor-clock|$5+;+dpll3_ck@d00ti,omap3-dpll-core-clock|x @ 05;dpll3_m3_ck@1140ti,divider-clock|x@5%;%dpll3_m3x2_mul_ckfixed-factor-clock|%5&;&dpll3_m3x2_ck@d00ti,gate-clock|& x 5';'emu_core_alwon_ckfixed-factor-clock|'5d;dsys_altclk fixed-clock50;0mcbsp_clks fixed-clock5;dpll3_m2_ck@d40ti,divider-clock|x @5;core_ckfixed-factor-clock|5(;(dpll1_fck@940ti,divider-clock|(x @5);)dpll1_ck@904ti,omap3-dpll-clock|)x  $ @ 45;dpll1_x2_ckfixed-factor-clock|5*;*dpll1_x2m2_ck@944ti,divider-clock|*x D5>;>cm_96m_fckfixed-factor-clock|+5,;,omap_96m_fck@d40 ti,mux-clock|,x @5G;Gdpll4_m3_ck@e40ti,divider-clock| x@5-;-dpll4_m3x2_mul_ckfixed-factor-clock|-5.;.dpll4_m3x2_ck@d00ti,gate-clock|.x 5/;/omap_54m_fck@d40 ti,mux-clock|/0x @5:;:cm_96m_d2_fckfixed-factor-clock|,51;1omap_48m_fck@d40 ti,mux-clock|10x @52;2omap_12m_fckfixed-factor-clock|25I;Idpll4_m4_ck@e40ti,divider-clock| x@53;3dpll4_m4x2_mul_ckti,fixed-factor-clock|3*54;4dpll4_m4x2_ck@d00ti,gate-clock|4x *5v;vdpll4_m5_ck@f40ti,divider-clock|?x@55;5dpll4_m5x2_mul_ckti,fixed-factor-clock|5*56;6dpll4_m5x2_ck@d00ti,gate-clock|6x *dpll4_m6_ck@1140ti,divider-clock|?x@57;7dpll4_m6x2_mul_ckfixed-factor-clock|758;8dpll4_m6x2_ck@d00ti,gate-clock|8x 59;9emu_per_alwon_ckfixed-factor-clock|95e;eclkout2_src_gate_ck@d70 ti,composite-no-wait-gate-clock|(x p5;;;clkout2_src_mux_ck@d70ti,composite-mux-clock|(,:x p5<;<clkout2_src_ckti,composite-clock|;<5=;=sys_clkout2@d70ti,divider-clock|=@x p=mpu_ckfixed-factor-clock|>5?;?arm_fck@924ti,divider-clock|?x $emu_mpu_alwon_ckfixed-factor-clock|?5f;fl3_ick@a40ti,divider-clock|(x @5@;@l4_ick@a40ti,divider-clock|@x @5A;Arm_ick@c40ti,divider-clock|Ax @gpt10_gate_fck@a00ti,composite-gate-clock| x 5C;Cgpt10_mux_fck@a40ti,composite-mux-clock|Bx @5D;Dgpt10_fckti,composite-clock|CDgpt11_gate_fck@a00ti,composite-gate-clock| x 5E;Egpt11_mux_fck@a40ti,composite-mux-clock|Bx @5F;Fgpt11_fckti,composite-clock|EFcore_96m_fckfixed-factor-clock|G5;mmchs2_fck@a00ti,wait-gate-clock|x 5;mmchs1_fck@a00ti,wait-gate-clock|x 5;i2c3_fck@a00ti,wait-gate-clock|x 5;i2c2_fck@a00ti,wait-gate-clock|x 5;i2c1_fck@a00ti,wait-gate-clock|x 5;mcbsp5_gate_fck@a00ti,composite-gate-clock| x 5;mcbsp1_gate_fck@a00ti,composite-gate-clock| x 5;core_48m_fckfixed-factor-clock|25H;Hmcspi4_fck@a00ti,wait-gate-clock|Hx 5;mcspi3_fck@a00ti,wait-gate-clock|Hx 5;mcspi2_fck@a00ti,wait-gate-clock|Hx 5;mcspi1_fck@a00ti,wait-gate-clock|Hx 5;uart2_fck@a00ti,wait-gate-clock|Hx 5;uart1_fck@a00ti,wait-gate-clock|Hx  5;core_12m_fckfixed-factor-clock|I5J;Jhdq_fck@a00ti,wait-gate-clock|Jx 5;core_l3_ickfixed-factor-clock|@5K;Ksdrc_ick@a10ti,wait-gate-clock|Kx 5w;wgpmc_fckfixed-factor-clock|Kcore_l4_ickfixed-factor-clock|A5L;Lmmchs2_ick@a10ti,omap3-interface-clock|Lx 5;mmchs1_ick@a10ti,omap3-interface-clock|Lx 5;hdq_ick@a10ti,omap3-interface-clock|Lx 5;mcspi4_ick@a10ti,omap3-interface-clock|Lx 5;mcspi3_ick@a10ti,omap3-interface-clock|Lx 5;mcspi2_ick@a10ti,omap3-interface-clock|Lx 5;mcspi1_ick@a10ti,omap3-interface-clock|Lx 5;i2c3_ick@a10ti,omap3-interface-clock|Lx 5;i2c2_ick@a10ti,omap3-interface-clock|Lx 5;i2c1_ick@a10ti,omap3-interface-clock|Lx 5;uart2_ick@a10ti,omap3-interface-clock|Lx 5;uart1_ick@a10ti,omap3-interface-clock|Lx  5;gpt11_ick@a10ti,omap3-interface-clock|Lx  5;gpt10_ick@a10ti,omap3-interface-clock|Lx  5;mcbsp5_ick@a10ti,omap3-interface-clock|Lx  5;mcbsp1_ick@a10ti,omap3-interface-clock|Lx  5;omapctrl_ick@a10ti,omap3-interface-clock|Lx 5;dss_tv_fck@e00ti,gate-clock|:x5;dss_96m_fck@e00ti,gate-clock|Gx5;dss2_alwon_fck@e00ti,gate-clock|x5;dummy_ck fixed-clockgpt1_gate_fck@c00ti,composite-gate-clock|x 5M;Mgpt1_mux_fck@c40ti,composite-mux-clock|Bx @5N;Ngpt1_fckti,composite-clock|MNaes2_ick@a10ti,omap3-interface-clock|Lx 5;wkup_32k_fckfixed-factor-clock|B5O;Ogpio1_dbck@c00ti,gate-clock|Ox 5;sha12_ick@a10ti,omap3-interface-clock|Lx 5;wdt2_fck@c00ti,wait-gate-clock|Ox 5;wdt2_ick@c10ti,omap3-interface-clock|Px 5;wdt1_ick@c10ti,omap3-interface-clock|Px 5;gpio1_ick@c10ti,omap3-interface-clock|Px 5;omap_32ksync_ick@c10ti,omap3-interface-clock|Px 5;gpt12_ick@c10ti,omap3-interface-clock|Px 5;gpt1_ick@c10ti,omap3-interface-clock|Px 5;per_96m_fckfixed-factor-clock|+5 ; per_48m_fckfixed-factor-clock|25Q;Quart3_fck@1000ti,wait-gate-clock|Qx 5};}gpt2_gate_fck@1000ti,composite-gate-clock|x5R;Rgpt2_mux_fck@1040ti,composite-mux-clock|Bx@5S;Sgpt2_fckti,composite-clock|RSgpt3_gate_fck@1000ti,composite-gate-clock|x5T;Tgpt3_mux_fck@1040ti,composite-mux-clock|Bx@5U;Ugpt3_fckti,composite-clock|TUgpt4_gate_fck@1000ti,composite-gate-clock|x5V;Vgpt4_mux_fck@1040ti,composite-mux-clock|Bx@5W;Wgpt4_fckti,composite-clock|VWgpt5_gate_fck@1000ti,composite-gate-clock|x5X;Xgpt5_mux_fck@1040ti,composite-mux-clock|Bx@5Y;Ygpt5_fckti,composite-clock|XYgpt6_gate_fck@1000ti,composite-gate-clock|x5Z;Zgpt6_mux_fck@1040ti,composite-mux-clock|Bx@5[;[gpt6_fckti,composite-clock|Z[gpt7_gate_fck@1000ti,composite-gate-clock|x5\;\gpt7_mux_fck@1040ti,composite-mux-clock|Bx@5];]gpt7_fckti,composite-clock|\]gpt8_gate_fck@1000ti,composite-gate-clock| x5^;^gpt8_mux_fck@1040ti,composite-mux-clock|Bx@5_;_gpt8_fckti,composite-clock|^_gpt9_gate_fck@1000ti,composite-gate-clock| x5`;`gpt9_mux_fck@1040ti,composite-mux-clock|Bx@5a;agpt9_fckti,composite-clock|`aper_32k_alwon_fckfixed-factor-clock|B5b;bgpio6_dbck@1000ti,gate-clock|bx5~;~gpio5_dbck@1000ti,gate-clock|bx5;gpio4_dbck@1000ti,gate-clock|bx5;gpio3_dbck@1000ti,gate-clock|bx5;gpio2_dbck@1000ti,gate-clock|bx 5;wdt3_fck@1000ti,wait-gate-clock|bx 5;per_l4_ickfixed-factor-clock|A5c;cgpio6_ick@1010ti,omap3-interface-clock|cx5;gpio5_ick@1010ti,omap3-interface-clock|cx5;gpio4_ick@1010ti,omap3-interface-clock|cx5;gpio3_ick@1010ti,omap3-interface-clock|cx5;gpio2_ick@1010ti,omap3-interface-clock|cx 5;wdt3_ick@1010ti,omap3-interface-clock|cx 5;uart3_ick@1010ti,omap3-interface-clock|cx 5;uart4_ick@1010ti,omap3-interface-clock|cx5;gpt9_ick@1010ti,omap3-interface-clock|cx 5;gpt8_ick@1010ti,omap3-interface-clock|cx 5;gpt7_ick@1010ti,omap3-interface-clock|cx5;gpt6_ick@1010ti,omap3-interface-clock|cx5;gpt5_ick@1010ti,omap3-interface-clock|cx5;gpt4_ick@1010ti,omap3-interface-clock|cx5;gpt3_ick@1010ti,omap3-interface-clock|cx5;gpt2_ick@1010ti,omap3-interface-clock|cx5;mcbsp2_ick@1010ti,omap3-interface-clock|cx5;mcbsp3_ick@1010ti,omap3-interface-clock|cx5;mcbsp4_ick@1010ti,omap3-interface-clock|cx5;mcbsp2_gate_fck@1000ti,composite-gate-clock|x5 ; mcbsp3_gate_fck@1000ti,composite-gate-clock|x5 ; mcbsp4_gate_fck@1000ti,composite-gate-clock|x5;emu_src_mux_ck@1140 ti,mux-clock|defx@5g;gemu_src_ckti,clkdm-gate-clock|g5h;hpclk_fck@1140ti,divider-clock|hx@pclkx2_fck@1140ti,divider-clock|hx@atclk_fck@1140ti,divider-clock|hx@traceclk_src_fck@1140 ti,mux-clock|defx@5i;itraceclk_fck@1140ti,divider-clock|i x@secure_32k_fck fixed-clock5j;jgpt12_fckfixed-factor-clock|jwdt1_fckfixed-factor-clock|jipss_ick@a10ti,am35xx-interface-clock|Kx 5;rmii_ck fixed-clock5;pclk_ck fixed-clock5;uart4_ick_am35xx@a10ti,omap3-interface-clock|Lx uart4_fck_am35xx@a00ti,wait-gate-clock|Hx dpll5_ck@d04ti,omap3-dpll-clock|x  $ L 4Se5k;kdpll5_m2_ck@d50ti,divider-clock|kx P5u;usgx_gate_fck@b00ti,composite-gate-clock|(x 5s;score_d3_ckfixed-factor-clock|(5l;lcore_d4_ckfixed-factor-clock|(5m;mcore_d6_ckfixed-factor-clock|(5n;nomap_192m_alwon_fckfixed-factor-clock|$5o;ocore_d2_ckfixed-factor-clock|(5p;psgx_mux_fck@b40ti,composite-mux-clock |lmn,opqrx @5t;tsgx_fckti,composite-clock|stsgx_ick@b10ti,wait-gate-clock|@x 5;cpefuse_fck@a08ti,gate-clock|x 5;ts_fck@a08ti,gate-clock|Bx 5;usbtll_fck@a08ti,wait-gate-clock|ux 5;usbtll_ick@a18ti,omap3-interface-clock|Lx 5;mmchs3_ick@a10ti,omap3-interface-clock|Lx 5;mmchs3_fck@a00ti,wait-gate-clock|x 5;dss1_alwon_fck_3430es2@e00ti,dss-gate-clock|vx*5;dss_ick_3430es2@e10ti,omap3-dss-interface-clock|Ax5;usbhost_120m_fck@1400ti,gate-clock|ux5;usbhost_48m_fck@1400ti,dss-gate-clock|2x5;usbhost_ick@1410ti,omap3-dss-interface-clock|Ax5;clockdomainscore_l3_clkdmti,clockdomain|wxyz{|dpll3_clkdmti,clockdomain|dpll1_clkdmti,clockdomain|per_clkdmti,clockdomainh|}~emu_clkdmti,clockdomain|hdpll4_clkdmti,clockdomain|wkup_clkdmti,clockdomain |dss_clkdmti,clockdomain|core_l4_clkdmti,clockdomain|dpll5_clkdmti,clockdomain|ksgx_clkdmti,clockdomain|usbhost_clkdmti,clockdomain |counter@48320000ti,omap-counter32kxH2  counter_32kinterrupt-controller@48200000ti,omap3-intcxH 5;dma-controller@48056000"ti,omap3630-sdmati,omap3430-sdmaxH` mx `5;gpio@48310000ti,omap3-gpioxH1gpio1gpio@49050000ti,omap3-gpioxIgpio2gpio@49052000ti,omap3-gpioxI gpio3gpio@49054000ti,omap3-gpioxI@ gpio4gpio@49056000ti,omap3-gpioxI`!gpio5gpio@49058000ti,omap3-gpioxI"gpio6serial@4806a000ti,omap3-uartxH H12txrxuart1lserial@4806c000ti,omap3-uartxHI34txrxuart2lserial@49020000ti,omap3-uartxIJ56txrxuart3li2c@48070000 ti,omap3-i2cxH8txrx+i2c1'@tps@2dx- ti,tps65910default  !-9EQregulators+regulator@0x^vrtcsregulator@1x^viosregulator@2x^vdd1 Jvdd_coreYOqOsregulator@3x^vdd2Jvdd_shvY2Zq2Zs5;regulator@4x^vdd3regulator@5x^vdig1regulator@6x^vdig2regulator@7x^vpllYw@qw@sregulator@8x^vdacYw@qw@sregulator@9x ^vaux1Yw@qw@sregulator@10x ^vaux2Yw@qw@sregulator@11x ^vaux33regulator@12x ^vmmcY2Zq2Zsregulator@13x ^vbbi2c@48072000 ti,omap3-i2cxH 9txrx+i2c2 disabledi2c@48060000 ti,omap3-i2cxH=txrx+i2c3 disabledmailbox@48094000ti,omap3-mailboxmailboxxH @ disableddsp  spi@48098000ti,omap2-mcspixH A+mcspi1@#$%&'()* tx0rx0tx1rx1tx2rx2tx3rx3spi@4809a000ti,omap2-mcspixH B+mcspi2 +,-.tx0rx0tx1rx1spi@480b8000ti,omap2-mcspixH [+mcspi3 tx0rx0tx1rx1spi@480ba000ti,omap2-mcspixH 0+mcspi4FGtx0rx01w@480b2000 ti,omap3-1wxH :hdq1wmmc@4809c000ti,omap3-hsmmcxH Smmc1=>txrxmmc@480b4000ti,omap3-hsmmcxH @Vmmc2/0txrx disabledmmc@480ad000ti,omap3-hsmmcxH ^mmc3MNtxrx disabledmmu@480bd400ti,omap2-iommuxH mmu_isp* disabledmmu@5d000000ti,omap2-iommux]mmu_iva disabledwdt@48314000 ti,omap3-wdtxH1@ wd_timer2mcbsp@48074000ti,omap3-mcbspxH@:mpu ;< DcommontxrxTmcbsp1 txrx|fck disabledmcbsp@49022000ti,omap3-mcbspxI I :mpusidetone>?DcommontxrxsidetoneTmcbsp2mcbsp2_sidetone!"txrx|fckick disabledmcbsp@49024000ti,omap3-mcbspxI@I :mpusidetoneYZDcommontxrxsidetoneTmcbsp3mcbsp3_sidetonetxrx|fckick disabledmcbsp@49026000ti,omap3-mcbspxI`:mpu 67 DcommontxrxTmcbsp4txrx|fck disabledmcbsp@48096000ti,omap3-mcbspxH `:mpu QR DcommontxrxTmcbsp5txrx|fck disabledsham@480c3000ti,omap3-shamshamxH 0d1Erxsmartreflex@480cb000ti,omap3-smartreflex-coresmartreflex_corexH smartreflex@480c9000ti,omap3-smartreflex-ivasmartreflex_mpu_ivaxH  disabledtimer@48318000ti,omap3430-timerxH1%timer1ctimer@49032000ti,omap3430-timerxI &timer2timer@49034000ti,omap3430-timerxI@'timer3timer@49036000ti,omap3430-timerxI`(timer4timer@49038000ti,omap3430-timerxI)timer5rtimer@4903a000ti,omap3430-timerxI*timer6rtimer@4903c000ti,omap3430-timerxI+timer7rtimer@4903e000ti,omap3430-timerxI,timer8rtimer@49040000ti,omap3430-timerxI-timer9timer@48086000ti,omap3430-timerxH`.timer10timer@48088000ti,omap3430-timerxH/timer11timer@48304000ti,omap3430-timerxH0@_timer12cusbhstll@48062000 ti,usbhs-tllxH N usb_tll_hsusbhshost@48064000ti,usbhs-hostxH@ usb_host_hs+ohci@48064400ti,ohci-omap3xHD Lehci@48064800 ti,ehci-omapxHH Mgpmc@6e000000ti,omap3430-gpmcgpmcxnrxtx+usb_otg_hs@480ab000ti,omap3-musbxH \]Dmcdma usb_otg_hs dss@48050000 ti,omap3-dssxH disabled dss_core|fck+dispc@48050400ti,omap3-dispcxH dss_dispc|fckencoder@4804fc00 ti,omap3-dsixHH@H :protophypll disabled dss_dsi1| fcksys_clkencoder@48050800ti,omap3-rfbixH disabled dss_rfbi|fckickencoder@48050c00ti,omap3-vencxH  disabled dss_venc|fckssi-controller@48058000 ti,omap3-ssissi disabledxHH:sysgddGDgdd_mpu+ssi-port@4805a000ti,omap3-ssi-portxHH:txrx CDssi-port@4805b000ti,omap3-ssi-portxHH:txrx EFam35x_otg_hs@5c040000ti,omap3-musb am35x_otg_hs disabledx\GDmcethernet@0x5c000000ti,am3517-emac davinci_emacokayx\CDEFC+ DWethernet@0x5c030000ti,davinci_mdio davinci_mdiookayx\iB@+serial@4809e000ti,omap3-uartuart4 disabledxH T76txrxlpinmux@480025d8 ti,omap3-padconfpinctrl-singlexH%$+memory@80000000lmemoryxfixedregulatorregulator-fixedJvbatYLK@qLK@5; compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2serial0serial1serial2serial3device_typeregclocksclock-namesclock-latencyinterruptsti,hwmodsstatusranges#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,pinslinux,phandlesysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lock#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedpinctrl-namespinctrl-0ti,en-ck32k-xtalvcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvccio-supplyregulator-compatibleregulator-always-onregulator-boot-on#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csti,dual-voltpbias-supplyvmmc-supplybus-width#iommu-cellsti,#tlb-entriesreg-namesinterrupt-namesti,buffer-sizeti,timer-alwonti,timer-dspti,timer-pwmti,timer-securegpmc,num-csgpmc,num-waitpinsmultipointnum-epsram-bitsti,davinci-ctrl-reg-offsetti,davinci-ctrl-mod-reg-offsetti,davinci-ctrl-ram-offsetti,davinci-ctrl-ram-sizeti,davinci-rmii-enlocal-mac-addressbus_freq