8@( vgoogle,veyron-mickey-rev8google,veyron-mickey-rev7google,veyron-mickey-rev6google,veyron-mickey-rev5google,veyron-mickey-rev4google,veyron-mickey-rev3google,veyron-mickey-rev2google,veyron-mickey-rev1google,veyron-mickey-rev0google,veyron-mickeygoogle,veyronrockchip,rk3288&7Google Mickeychosenaliases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff140000Q/i2c@ff660000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/dwmmc@ff0f0000k/dwmmc@ff0c0000q/dwmmc@ff0d0000w/dwmmc@ff0e0000}/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000memorymemoryarm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500cpuarm,cortex-a12hw@\@p@ @@OOa sB@ ~ ' 9 K 0 $@29EKcpu@501cpuarm,cortex-a12EKcpu@502cpuarm,cortex-a12EKcpu@503cpuarm,cortex-a12EKamba simple-busSdma-controller@ff250000arm,pl330arm,primecell%@Ze2 apb_pclkEKdma-controller@ff600000arm,pl330arm,primecell`@Ze2 apb_pclk disableddma-controller@ffb20000arm,pl330arm,primecell@Ze2 apb_pclkEHKHreserved-memorySdma-unusable@fe000000oscillator fixed-clockn6xin24mE K timerarm,armv7-timer0   n6timer@ff810000rockchip,rk3288-timer  H 2 a timerpclkdisplay-subsystemrockchip,display-subsystem dwmmc@ff0c0000rockchip,rk3288-dw-mshcр 2Drvbiuciuciu-driveciu-sample  @ disableddwmmc@ff0d0000rockchip,rk3288-dw-mshcр 2Eswbiuciuciu-driveciu-sample ! @okay",=J` kydefault  dwmmc@ff0e0000rockchip,rk3288-dw-mshcр 2Ftxbiuciuciu-driveciu-sample "@ disableddwmmc@ff0f0000rockchip,rk3288-dw-mshcр 2Guybiuciuciu-driveciu-sample #@okay"$`kydefault saradc@ff100000rockchip,saradc $32I[saradcapb_pclkW Esaradc-apb disabledspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spi2ARspiclkapb_pclkQ  Vtxrx ,default disabledspi@ff120000(rockchip,rk3288-spirockchip,rk3066-spi2BSspiclkapb_pclkQ Vtxrx -default disabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spi2CTspiclkapb_pclkQVtxrx .default !"okay` flash@0jedec,spi-norsi2c@ff140000rockchip,rk3288-i2c >i2c2Mdefault#okay2dtpm@20infineon,slb9645tt i2c@ff150000rockchip,rk3288-i2c ?i2c2Odefault$ disabledi2c@ff160000rockchip,rk3288-i2c @i2c2Pdefault% disabled2,i2c@ff170000rockchip,rk3288-i2c Ai2c2Qdefault&okay,EYKYserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart 72MUbaudclkapb_pclkdefault '()okayMlserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart 82NVbaudclkapb_pclkdefault*okayserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uarti 92OWbaudclkapb_pclkdefault+okayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart :2PXbaudclkapb_pclkdefault, disabledserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart ;2QYbaudclkapb_pclkdefault- disabledthermal-zonesreserve_thermal,.cpu_thermald,.tripscpu_crit<_H criticalcpu_alert_almost_warm<Hpassivecpu_alert_warm<HpassiveE/K/cpu_alert_almost_hot<8HpassiveE0K0cpu_alert_hot<@PHpassiveE1K1cpu_alert_hotter<H HpassiveE2K2cpu_alert_very_hot<LHpassiveE3K3cooling-mapscpu_warm_limit_cpuS/ Xcpu_almost_hot_limit_cpuS0 Xcpu_hot_limit_cpuS1 Xcpu_hotter_limit_cpuS2 Xcpu_very_hot_limit_cpuS3 Xgpu_thermald,.tripsgpu_alert0<pHpassiveE4K4gpu_crit<_H criticalcooling-mapsmap0S4 Xtsadc@ff280000rockchip,rk3288-tsadc( %2HZtsadcapb_pclk Etsadc-apbinitdefaultsleep5g6q5{sokayE.K.ethernet@ff290000rockchip,rk3288-gmac)macirqeth_wake_irq782fgc]Mstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macB Estmmaceth disabledusb@ff500000 generic-ehciP 2usbhost8usb disabledusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2T 2otghost9 usb2-phy disabledusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2X 2otghost$6E@@ T: usb2-phyokayz^:usb@ff5c0000 generic-ehci\ 2usbhost disabledi2c@ff650000rockchip,rk3288-i2ce <i2c2Ldefault;okay2dpmic@1brockchip,rk808xin32kwifibt_32kin&<default =>?u@A AEhKhregulatorsDCDC_REG1vdd_arm3E q] uqEKregulator-state-memDCDC_REG2vdd_gpu3E 5]uqE]K]regulator-state-memB@DCDC_REG3 vcc135_ddr3regulator-state-memDCDC_REG4vcc_183Ew@]w@EKregulator-state-memw@LDO_REG3vdd_103EB@]B@regulator-state-memB@LDO_REG7 vdd10_lcd3EB@]B@SWITCH_REG1 vcc33_lcd3EGKGregulator-state-memLDO_REG83Ew@]w@ vcc18_lcdi2c@ff660000rockchip,rk3288-i2cf =i2c2NdefaultB disabled2 pwm@ff680000rockchip,rk3288-pwmhdefaultC2^pwm disabledpwm@ff680010rockchip,rk3288-pwmhdefaultD2^pwmokaypwm@ff680020rockchip,rk3288-pwmh defaultE2^pwm disabledpwm@ff680030rockchip,rk3288-pwmh0defaultF2^pwm disabledbus_intmem@ff700000 mmio-sramp Spsmp-sram@0rockchip,rk3066-smp-sramsram@ff720000#rockchip,rk3288-pmu-srammmio-sramrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfdsEKpower-controller!rockchip,rk3288-power-controllerh^ EKKKpd_vio@9 2chgfdehilkjpd_hevc@11 2oppd_video@12 2pd_gpu@13 2reboot-modesyscon-reboot-modeRB(RB6RB FRBsyscon@ff740000rockchip,rk3288-sgrfsyscontclock-controller@ff760000rockchip,rk3288-cruv7RHjk$#gׄeрxhрxhEKsyscon@ff770000&rockchip,rk3288-grfsysconsimple-mfdwE7K7edp-phyrockchip,rk3288-dp-phy2h24m_ disabledEVKVio-domains"rockchip,rk3288-io-voltage-domainokayj@t@@Gusbphyrockchip,rk3288-usb-phyokayusb-phy@320_ 2]phyclkE:K:usb-phy@334_42^phyclkE8K8usb-phy@348_H2_phyclkE9K9watchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt2p Ookaysound@ff88b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif hclkmclk2TQHVtx 6defaultI7 disabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s 5QHHVtxrxi2s_hclki2s_clki2s_clk_out2RqdefaultJokaycypto-controller@ff8a0000rockchip,rk3288-crypto@ 0 2}aclkhclksclkapb_pclk Ecrypto-rstokayvop@ff930000rockchip,rk3288-vop 2aclk_vopdclk_vophclk_vop K def EaxiahbdclkLokayportE K endpoint@0MEZKZendpoint@1NEWKWendpoint@2OETKTiommu@ff930300rockchip,iommu  vopb_mmu K .okayELKLvop@ff940000rockchip,rk3288-vop 2aclk_vopdclk_vophclk_vop K  EaxiahbdclkP disabledportE K endpoint@0QE[K[endpoint@1REXKXendpoint@2SEUKUiommu@ff940300rockchip,iommu  vopl_mmu K . disabledEPKPmipi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi@ 2~d refpclk K 7 disabledportsportendpoint@0TEOKOendpoint@1UESKSdp@ff970000rockchip,rk3288-dp@ b2icdppclkVdpoEdp7 disabledportsport@0endpoint@0WENKNendpoint@1XERKRhdmi@ff980000rockchip,rk3288-dw-hdmi7 g2hm iahbisfr K okay;Yportsportendpoint@0ZEMKMendpoint@1[EQKQmali@ffa300004rockchip,rk3288-maliarm,mali-t760arm,mali-midgard$ jobmmugpu2G\ K okay[]gpu-opp-tableoperating-points-v2E\K\opp@100000000gn~opp@200000000g n~opp@300000000gnB@opp@400000000gׄnopp@500000000genOopp@600000000g#Fninterrupt-controller@ffc01000 arm,gic-400|  @ `   EKefuse@ffb40000rockchip,rockchip-efuse 2q pclk_efusecpu_leakage@17pinctrlrockchip,rk3288-pinctrl7Sdefaultsleep^g^gpio0@ff750000rockchip,gpio-banku Q2@|E<K<gpio1@ff780000rockchip,gpio-bankx R2A|gpio2@ff790000rockchip,gpio-banky S2B|EgKggpio3@ff7a0000rockchip,gpio-bankz T2C|gpio4@ff7b0000rockchip,gpio-bank{ U2D|EkKkgpio5@ff7c0000rockchip,gpio-bank| V2E|gpio6@ff7d0000rockchip,gpio-bank} W2F|gpio7@ff7e0000rockchip,gpio-bank~ X2G|EAKAgpio8@ff7f0000rockchip,gpio-bank Y2H|hdmihdmi-ddc __power-hdmi-on _EmKmpcfg-pull-upE`K`pcfg-pull-downEaKapcfg-pull-noneE_K_pcfg-pull-none-12ma EcKcsleepglobal-pwroff_E^K^ddrio-pwroff_ddr0-retention`ddr1-retention`edpedp-hpd ai2c0i2c0-xfer __E;K;i2c1i2c1-xfer __E#K#i2c2i2c2-xfer  _ _EBKBi2c3i2c3-xfer __E$K$i2c4i2c4-xfer __E%K%i2c5i2c5-xfer __E&K&i2s0i2s0-bus`______EJKJsdmmcsdmmc-clk_sdmmc-cmd`sdmmc-cd`sdmmc-bus1`sdmmc-bus4@````sdio0sdio0-bus1`sdio0-bus4@bbbbEKsdio0-cmdbEKsdio0-clkbE K sdio0-cd`sdio0-wp`sdio0-pwr`sdio0-bkpwr`sdio0-int`wifienable-h_EjKjbt-enable-l_EiKisdio1sdio1-bus1`sdio1-bus4@````sdio1-cd`sdio1-wp`sdio1-bkpwr`sdio1-int`sdio1-cmd`sdio1-clk_sdio1-pwr `emmcemmc-clkbEKemmc-cmdbEKemmc-pwr `emmc-bus1`emmc-bus4@````emmc-bus8bbbbbbbbEKemmc-reset _EfKfspi0spi0-clk `EKspi0-cs0 `EKspi0-tx`EKspi0-rx`EKspi0-cs1`spi1spi1-clk `EKspi1-cs0 `EKspi1-rx`EKspi1-tx`EKspi2spi2-cs1`spi2-clk`EKspi2-cs0`E"K"spi2-rx`E!K!spi2-tx `E K uart0uart0-xfer `_E'K'uart0-cts`E(K(uart0-rts_E)K)uart1uart1-xfer ` _E*K*uart1-cts `uart1-rts _uart2uart2-xfer `_E+K+uart3uart3-xfer `_E,K,uart3-cts `uart3-rts _uart4uart4-xfer  ` _E-K-uart4-cts`uart4-rts_tsadcotp-gpio _E5K5otp-out _E6K6pwm0pwm0-pin_ECKCpwm1pwm1-pin_EDKDpwm2pwm2-pin_EEKEpwm3pwm3-pin_EFKFgmacrgmii-pins____cccc___ cc__rmii-pins__________spdifspdif-tx _EIKIpcfg-pull-none-drv-8maEbKbpcfg-pull-up-drv-8mapcfg-output-high pcfg-output-low buttonspwr-key-l`EdKdpmicpmic-int-l`E=K=dvs-1 aE>K>dvs-2aE?K?rebootap-warm-reset-h _EeKerecovery-switchrec-mode-l `tpmtpm-int-h_write-protectfw-wp-ap_gpio-keys gpio-keysdefaultdpower Power < !t ,dgpio-restart gpio-restart < defaulte >emmc-pwrseqmmc-pwrseq-emmcfdefault Gg EKsdio-pwrseqmmc-pwrseq-simple2h ext_clockdefaultij GkE K vcc-5vregulator-fixedvcc_5v3ELK@]LK@ SElKlvcc33-sysregulator-fixed vcc33_sys3E2Z]2ZEKvcc50-hdmiregulator-fixed vcc50_hdmi3 Sl ^ qA defaultmvcc33_ioregulator-fixed vcc33_io3 SE@K@ #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2device_typereginterruptsinterrupt-affinityenable-methodrockchip,pmuresetsoperating-points#cooling-cellsclock-latencyclockscpu0-supplylinux,phandleranges#dma-cellsarm,pl330-broken-no-flushpclock-namesstatusclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredarm,no-tick-in-suspendportsclock-freq-min-maxfifo-depthbus-widthcap-sd-highspeedcap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablenum-slotspinctrl-namespinctrl-0sd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplycap-mmc-highspeedrockchip,default-sample-phasedisable-wpmmc-hs200-1_8v#io-channel-cellsreset-namesdmasdma-namesrx-sample-delay-nsspi-max-frequencyi2c-scl-falling-time-nsi2c-scl-rising-time-nspowered-while-suspendedreg-shiftreg-io-widthassigned-clocksassigned-clock-ratespolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesrockchip,grfphysphy-namesneeds-reset-on-resumedr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeg-use-dmaassigned-clock-parentsrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc7-supplyvcc8-supplyvddio-supplydvs-gpiosvcc11-supplyregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvoltregulator-suspend-mem-disabled#pwm-cells#power-domain-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cells#phy-cellsbb-supplydvp-supplyflash0-supplygpio1830-supplygpio30-supplylcdc-supplywifi-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channelspower-domainsiommusremote-endpoint#iommu-cellsddc-i2c-busoperating-points-v2mali-supplyopp-hzopp-microvoltinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsrockchip,pinsbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowlabellinux,codedebounce-intervalpriorityreset-gpiosvin-supplyenable-active-highgpio