t8~(~mqmaker,miqirockchip,rk3288& 7mqmaker MiQichosen=serial2:115200n8aliasesI/ethernet@ff290000S/i2c@ff650000X/i2c@ff140000]/i2c@ff660000b/i2c@ff150000g/i2c@ff160000l/i2c@ff170000q/dwmmc@ff0f0000w/dwmmc@ff0c0000}/dwmmc@ff0d0000/dwmmc@ff0e0000/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000memorymemoryarm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500cpuarm,cortex-a12 `@p@ @OOa sB@ ~ ' 9  K 0 !0@>EQWcpu@501cpuarm,cortex-a12 QWcpu@502cpuarm,cortex-a12 QWcpu@503cpuarm,cortex-a12 QWamba simple-bus_dma-controller@ff250000arm,pl330arm,primecell%@fq> apb_pclkQWdma-controller@ff600000arm,pl330arm,primecell`@fq> apb_pclk disableddma-controller@ffb20000arm,pl330arm,primecell@fq> apb_pclkQJWJreserved-memory_dma-unusable@fe000000oscillator fixed-clockn6xin24mQ W timerarm,armv7-timer0   n6timer@ff810000rockchip,rk3288-timer  H > a timerpclkdisplay-subsystemrockchip,display-subsystem dwmmc@ff0c0000rockchip,rk3288-dw-mshcр >Drvbiuciuciu-driveciu-sample#  @okay.8J[mxdefault dwmmc@ff0d0000rockchip,rk3288-dw-mshcр >Eswbiuciuciu-driveciu-sample# ! @ disableddwmmc@ff0e0000rockchip,rk3288-dw-mshcр >Ftxbiuciuciu-driveciu-sample# "@ disableddwmmc@ff0f0000rockchip,rk3288-dw-mshcр >Guybiuciuciu-driveciu-sample# #@okay.8mxdefaultsaradc@ff100000rockchip,saradc $>I[saradcapb_pclk W saradc-apbokayspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spi>ARspiclkapb_pclk  txrx ,default disabledspi@ff120000(rockchip,rk3288-spirockchip,rk3066-spi>BSspiclkapb_pclk txrx -default ! disabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spi>CTspiclkapb_pclktxrx .default"#$% disabledi2c@ff140000rockchip,rk3288-i2c >i2c>Mdefault&okayi2c@ff150000rockchip,rk3288-i2c ?i2c>Odefault' disabledi2c@ff160000rockchip,rk3288-i2c @i2c>Pdefault(okayi2c@ff170000rockchip,rk3288-i2c Ai2c>Qdefault)okayQ[W[serial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart 7>MUbaudclkapb_pclkdefault* disabledserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart 8>NVbaudclkapb_pclkdefault+ disabledserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uarti 9>OWbaudclkapb_pclkdefault,okayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart :>PXbaudclkapb_pclkdefault-okayserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart ;>QYbaudclkapb_pclkdefault. disabledthermal-zonesreserve_thermal'5/cpu_thermald'5/tripscpu_alert0EpQpassiveQ0W0cpu_alert1E$QpassiveQ1W1cpu_critE_Q criticalcooling-mapsmap0\0 amap1\1 agpu_thermald'5/tripsgpu_alert0EpQpassiveQ2W2gpu_critE_Q criticalcooling-mapsmap0\2 atsadc@ff280000rockchip,rk3288-tsadc( %>HZtsadcapb_pclk  tsadc-apbinitdefaultsleep3p4z3sokayQ/W/ethernet@ff290000rockchip,rk3288-gmac)macirqeth_wake_irq58>fgc]Mstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac B stmmacethok6'inputdefault789:4;?rgmiiH ^'B@ s<0usb@ff500000 generic-ehciP >usbhost=usb disabledusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2T >otghost> usb2-phyokayusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2X >otg peripheral@@ ? usb2-phyokayusb@ff5c0000 generic-ehci\ >usbhost disabledi2c@ff650000rockchip,rk3288-i2ce <i2c>Ldefault@okaysyr827@40silergy,syr827@vdd_cpu P*pBVh,@AQWsyr828@41silergy,syr828Avdd_gpu P*pBAhym8563@51haoyu,hym8563Qxin32kact8846@5aactive-semi,act8846ZdefaultBAAAAAACregulatorsREG1vcc_ddrBREG2vcc_io2Z*2ZBQWREG3vdd_log*BREG4vcc_20*BQCWCREG5 vccio_sd2Z*2ZBQWREG6 vdd10_lcdB@*B@BREG7vcca_18w@*w@REG8vcca_332Z*2ZQIWIREG9vcc_lan2Z*2ZQ;W;REG10vdd_10B@*B@BREG11vcc_18w@*w@BQWREG12 vcc18_lcdw@*w@Bi2c@ff660000rockchip,rk3288-i2cf =i2c>NdefaultDokaypwm@ff680000rockchip,rk3288-pwmh defaultE>^pwm disabledpwm@ff680010rockchip,rk3288-pwmh defaultF>^pwm disabledpwm@ff680020rockchip,rk3288-pwmh  defaultG>^pwm disabledpwm@ff680030rockchip,rk3288-pwmh0 defaultH>^pwm disabledbus_intmem@ff700000 mmio-sramp _psmp-sram@0rockchip,rk3066-smp-sramsram@ff720000#rockchip,rk3288-pmu-srammmio-sramrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfdsQWpower-controller!rockchip,rk3288-power-controllerh QMWMpd_vio@9 >chgfdehilkjpd_hevc@11 >oppd_video@12 >pd_gpu@13 >reboot-modesyscon-reboot-mode+2RB>RBLRB \RBsyscon@ff740000rockchip,rk3288-sgrfsyscontclock-controller@ff760000rockchip,rk3288-cruv5hHjk$u#gׄeрxhрxhQWsyscon@ff770000&rockchip,rk3288-grfsysconsimple-mfdwQ5W5edp-phyrockchip,rk3288-dp-phy>h24m disabledQXWXio-domains"rockchip,rk3288-io-voltage-domainokayI;usbphyrockchip,rk3288-usb-phyokayusb-phy@320 >]phyclkQ?W?usb-phy@3344>^phyclkQ=W=usb-phy@348H>_phyclkQ>W>watchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt>p Ookaysound@ff88b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif hclkmclk>TJtx 6defaultK5 disabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s 5JJtxrxi2s_hclki2s_clk>RdefaultL. disabledcypto-controller@ff8a0000rockchip,rk3288-crypto@ 0 >}aclkhclksclkapb_pclk  crypto-rstokayvop@ff930000rockchip,rk3288-vop >aclk_vopdclk_vophclk_vopHM  def axiahbdclkVNokayportQ W endpoint@0]OQ\W\endpoint@1]PQYWYendpoint@2]QQVWViommu@ff930300rockchip,iommu  vopb_mmuHM mokayQNWNvop@ff940000rockchip,rk3288-vop >aclk_vopdclk_vophclk_vopHM   axiahbdclkVRokayportQ W endpoint@0]SQ]W]endpoint@1]TQZWZendpoint@2]UQWWWiommu@ff940300rockchip,iommu  vopl_mmuHM mokayQRWRmipi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi@ >~d refpclkHM 5 disabledportsportendpoint@0]VQQWQendpoint@1]WQUWUdp@ff970000rockchip,rk3288-dp@ b>icdppclkXdp odp5 disabledportsport@0endpoint@0]YQPWPendpoint@1]ZQTWThdmi@ff980000rockchip,rk3288-dw-hdmi5 g>hm iahbisfrHM okayz[portsportendpoint@0]\QOWOendpoint@1]]QSWSmali@ffa300004rockchip,rk3288-maliarm,mali-t760arm,mali-midgard$ jobmmugpu>^HM  disabledgpu-opp-tableoperating-points-v2Q^W^opp@100000000~opp@200000000 ~opp@300000000B@opp@400000000ׄopp@500000000eOopp@600000000#Finterrupt-controller@ffc01000 arm,gic-400  @ `   QWefuse@ffb40000rockchip,rockchip-efuse >q pclk_efusecpu_leakage@17pinctrlrockchip,rk3288-pinctrl5_gpio0@ff750000rockchip,gpio-banku Q>@QhWhgpio1@ff780000rockchip,gpio-bankx R>Agpio2@ff790000rockchip,gpio-banky S>Bgpio3@ff7a0000rockchip,gpio-bankz T>Cgpio4@ff7b0000rockchip,gpio-bank{ U>DQ<W<gpio5@ff7c0000rockchip,gpio-bank| V>Egpio6@ff7d0000rockchip,gpio-bank} W>Fgpio7@ff7e0000rockchip,gpio-bank~ X>GQfWfgpio8@ff7f0000rockchip,gpio-bank Y>Hhdmihdmi-ddc __pcfg-pull-upQ`W`pcfg-pull-down QaWapcfg-pull-noneQ_W_pcfg-pull-none-12ma( QbWbsleepglobal-pwroff_ddrio-pwroff_ddr0-retention`ddr1-retention`edpedp-hpd ai2c0i2c0-xfer __Q@W@i2c1i2c1-xfer __Q&W&i2c2i2c2-xfer  _ _QDWDi2c3i2c3-xfer __Q'W'i2c4i2c4-xfer __Q(W(i2c5i2c5-xfer __Q)W)i2s0i2s0-bus`______QLWLsdmmcsdmmc-clkbQ W sdmmc-cmdcQ W sdmmc-cd`QWsdmmc-bus1`sdmmc-bus4@ccccQWsdmmc-pwr _QjWjsdio0sdio0-bus1`sdio0-bus4@````sdio0-cmd`sdio0-clk_sdio0-cd`sdio0-wp`sdio0-pwr`sdio0-bkpwr`sdio0-int`sdio1sdio1-bus1`sdio1-bus4@````sdio1-cd`sdio1-wp`sdio1-bkpwr`sdio1-int`sdio1-cmd`sdio1-clk_sdio1-pwr `emmcemmc-clk_QWemmc-cmd`QWemmc-pwr `QWemmc-bus1`emmc-bus4@````emmc-bus8````````QWspi0spi0-clk `QWspi0-cs0 `QWspi0-tx`QWspi0-rx`QWspi0-cs1`spi1spi1-clk `QWspi1-cs0 `Q!W!spi1-rx`Q W spi1-tx`QWspi2spi2-cs1`spi2-clk`Q"W"spi2-cs0`Q%W%spi2-rx`Q$W$spi2-tx `Q#W#uart0uart0-xfer `_Q*W*uart0-cts`uart0-rts_uart1uart1-xfer ` _Q+W+uart1-cts `uart1-rts _uart2uart2-xfer `_Q,W,uart3uart3-xfer `_Q-W-uart3-cts `uart3-rts _uart4uart4-xfer  ` _Q.W.uart4-cts`uart4-rts_tsadcotp-gpio _Q3W3otp-out _Q4W4pwm0pwm0-pin_QEWEpwm1pwm1-pin_QFWFpwm2pwm2-pin_QGWGpwm3pwm3-pin_QHWHgmacrgmii-pins____bbbb___ bb__Q7W7rmii-pins__________phy-int `Q:W:phy-pmeb`Q9W9phy-rstdQ8W8spdifspdif-tx _QKWKpcfg-output-high7QdWdpcfg-output-lowCQeWepcfg-pull-up-drv-12ma( QcWcact8846pmic-int`pmic-sleepepmic-vseleQBWBledsled-ctl_QgWgusb_hosthost-vbus-drv_QiWiexternal-gmac-clock fixed-clocksY@ ext_gmacQ6W6leds gpio-ledswork NfTmiqi:green:user Zdefault-ondefaultgflash-regulatorregulator-fixed vcc_flashw@*w@QWusb-host-regulatorregulator-fixedp ~hdefaulti vcc_hostLK@*LK@BAsdmmc-regulatorregulator-fixed ~f defaultjvcc_sd2Z*2ZQWvsys-regulatorregulator-fixedvcc_sysLK@*LK@BVQAWA #address-cells#size-cellscompatibleinterrupt-parentmodelstdout-pathethernet0i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2device_typereginterruptsinterrupt-affinityenable-methodrockchip,pmuresetsoperating-points#cooling-cellsclock-latencyclockscpu0-supplylinux,phandleranges#dma-cellsarm,pl330-broken-no-flushpclock-namesstatusclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredarm,no-tick-in-suspendportsclock-freq-min-maxfifo-depthbus-widthcap-mmc-highspeedcap-sd-highspeedcard-detect-delaydisable-wpnum-slotspinctrl-namespinctrl-0vmmc-supplyvqmmc-supplynon-removable#io-channel-cellsreset-namesvref-supplydmasdma-namesreg-shiftreg-io-widthpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesrockchip,grfassigned-clocksassigned-clock-parentsclock_in_outphy-supplyphy-modesnps,reset-active-lowsnps,reset-delays-ussnps,reset-gpiotx_delayrx_delayphysphy-namesdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeg-use-dmafcs,suspend-voltage-selectorregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-onregulator-enable-ramp-delayregulator-ramp-delayvin-supplysystem-power-controllervp1-supplyvp2-supplyvp3-supplyvp4-supplyinl1-supplyinl2-supplyinl3-supply#pwm-cells#power-domain-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cellsaudio-supplyflash0-supplyflash1-supplygpio30-supplygpio1830-supplylcdc-supplysdcard-supplywifi-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channelspower-domainsiommusremote-endpoint#iommu-cellsddc-i2c-busoperating-points-v2opp-hzopp-microvoltinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsrockchip,pinsbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowgpioslabellinux,default-triggerenable-active-highstartup-delay-us